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cores/uart: add txempty/rxfull CSRs. 

Useful in some use cases, like flushing tx.
This commit is contained in:
Florent Kermarrec 2020-08-04 13:49:50 +02:00
parent 2a3e39b10e
commit e0f131a317
1 changed files with 5 additions and 0 deletions
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5
litex/soc/cores/uart.py
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@ -201,6 +201,9 @@ class UART(Module, AutoCSR, UARTInterface):
self.ev.rx = EventSourceProcess() self.ev.rx = EventSourceProcess()
self.ev.finalize() self.ev.finalize()
self._txempty = CSRStatus()
self._rxfull = CSRStatus()
# # # # # #
UARTInterface.__init__(self) UARTInterface.__init__(self)
@ -220,6 +223,7 @@ class UART(Module, AutoCSR, UARTInterface):
tx_fifo.sink.valid.eq(self._rxtx.re), tx_fifo.sink.valid.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r), tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ready), self._txfull.status.eq(~tx_fifo.sink.ready),
self._txempty.status.eq(~tx_fifo.source.valid),
tx_fifo.source.connect(self.source), tx_fifo.source.connect(self.source),
# Generate TX IRQ when tx_fifo becomes non-full # Generate TX IRQ when tx_fifo becomes non-full
self.ev.tx.trigger.eq(~tx_fifo.sink.ready) self.ev.tx.trigger.eq(~tx_fifo.sink.ready)
@ -232,6 +236,7 @@ class UART(Module, AutoCSR, UARTInterface):
self.comb += [ self.comb += [
self.sink.connect(rx_fifo.sink), self.sink.connect(rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.valid), self._rxempty.status.eq(~rx_fifo.source.valid),
self._rxfull.status.eq(~rx_fifo.sink.ready),
self._rxtx.w.eq(rx_fifo.source.data), self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)), rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)),
# Generate RX IRQ when rx_fifo becomes non-empty # Generate RX IRQ when rx_fifo becomes non-empty