soc: move uart to a single file

litex/soc/cores/uart.py

@@ -5,6 +5,7 @@ from litex.gen.genlib.cdc import MultiReg
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *
 from litex.soc.interconnect import stream
+from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
 
 
 class RS232PHYRX(Module):
@@ -176,3 +177,9 @@ class UART(Module, AutoCSR):
             # Generate RX IRQ when tx_fifo becomes non-empty
             self.ev.rx.trigger.eq(~rx_fifo.source.valid)
         ]
+
+
+class UARTWishboneBridge(WishboneStreamingBridge):
+    def __init__(self, pads, clk_freq, baudrate=115200):
+        self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
+        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

litex/soc/cores/uart/__init__.py

@@ -1 +0,0 @@
-from litex.soc.cores.uart.core import UART, RS232PHY, RS232PHYModel

litex/soc/cores/uart/bridge.py

@@ -1,10 +0,0 @@
-from litex.gen import *
-
-from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
-from litex.soc.cores.uart.core import RS232PHY
-
-
-class UARTWishboneBridge(WishboneStreamingBridge):
-    def __init__(self, pads, clk_freq, baudrate=115200):
-        self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
-        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)