targets/simple: add MiniSoC
This commit is contained in:
parent
95fa753149
commit
e133777450
|
@ -2,6 +2,8 @@ from migen.fhdl.std import *
|
|||
from migen.bus import wishbone
|
||||
|
||||
from misoclib.soc import SoC, mem_decoder
|
||||
from misoclib.com.liteeth.phy import LiteEthPHY
|
||||
from misoclib.com.liteeth.mac import LiteEthMAC
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, clk_in):
|
||||
|
@ -17,7 +19,7 @@ class _CRG(Module):
|
|||
self.cd_sys.rst.eq(~rst_n)
|
||||
]
|
||||
|
||||
class SimpleSoC(SoC):
|
||||
class BaseSoC(SoC):
|
||||
def __init__(self, platform, **kwargs):
|
||||
SoC.__init__(self, platform,
|
||||
clk_freq=int((1/(platform.default_clk_period))*1000000000),
|
||||
|
@ -27,4 +29,29 @@ class SimpleSoC(SoC):
|
|||
clk_in = platform.request(platform.default_clk_name)
|
||||
self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
|
||||
|
||||
default_subtarget = SimpleSoC
|
||||
class MiniSoC(BaseSoC):
|
||||
csr_map = {
|
||||
"ethphy": 20,
|
||||
"ethmac": 21
|
||||
}
|
||||
csr_map.update(BaseSoC.csr_map)
|
||||
|
||||
interrupt_map = {
|
||||
"ethmac": 2,
|
||||
}
|
||||
interrupt_map.update(BaseSoC.interrupt_map)
|
||||
|
||||
mem_map = {
|
||||
"ethmac": 0x30000000, # (shadow @0xb0000000)
|
||||
}
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
def __init__(self, platform, **kwargs):
|
||||
BaseSoC.__init__(self, platform, **kwargs)
|
||||
|
||||
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
|
||||
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
|
||||
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
|
||||
|
||||
default_subtarget = BaseSoC
|
||||
|
|
Loading…
Reference in New Issue