cpu/cva6: Only keep AXI<->AXI-Lite conversion.
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@ -79,27 +79,20 @@ class CVA6(CPU):
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"csr" : 0x80000000
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"csr" : 0x80000000
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}
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}
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def __init__(self, platform, variant="standard", use_wishbone=True):
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.platform = platform
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self.variant = variant
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self.variant = variant
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self.reset = Signal()
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self.reset = Signal()
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self.interrupt = Signal(32)
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self.interrupt = Signal(32)
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if use_wishbone:
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self.axi_lite_if = axi.AXILiteInterface(data_width=64, address_width=32)
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self.wb_if = wishbone.Interface(data_width=64, adr_width=29)
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self.periph_buses = [self.axi_lite_if] # Peripheral buses (Connected to main SoC's bus).
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self.periph_buses = [self.wb_if] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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else:
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self.axi_lite_if = axi.AXILiteInterface(data_width=64, address_width=32)
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self.periph_buses = [self.axi_lite_if] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# # #
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# # #
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# AXI <-> Wishbone/AXILite conversion.
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# AXI <-> AXILite conversion.
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axi_if = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
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axi_if = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
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if use_wishbone:
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self.submodules += axi.AXI2AXILite(axi_if, self.axi_lite_if)
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self.submodules += axi.AXI2Wishbone(axi_if, self.wb_if)
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else:
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self.submodules += axi.AXI2AXILite(axi_if, self.axi_lite_if)
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# CPU Instance.
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# CPU Instance.
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self.cpu_params = dict(
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self.cpu_params = dict(
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@ -107,9 +100,6 @@ class CVA6(CPU):
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i_clk_i = ClockSignal("sys"),
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i_clk_i = ClockSignal("sys"),
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i_rst_n = ~ResetSignal("sys") | self.reset,
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i_rst_n = ~ResetSignal("sys") | self.reset,
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# Interrupts.
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i_irq_sources = self.interrupt,
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# AXI interface.
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# AXI interface.
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o_AWVALID_o = axi_if.aw.valid,
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o_AWVALID_o = axi_if.aw.valid,
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i_AWREADY_i = axi_if.aw.ready,
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i_AWREADY_i = axi_if.aw.ready,
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