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soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.

This commit is contained in:
Florent Kermarrec 2020-05-11 22:39:17 +02:00
parent 1e610600f6
commit e2176cefc2
2 changed files with 13 additions and 18 deletions
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4
litex/soc/integration/soc.py
View File

@ -758,8 +758,8 @@ class SoC(Module):
def add_csr_bridge(self, origin): def add_csr_bridge(self, origin):
self.submodules.csr_bridge = wishbone2csr.WB2CSR( self.submodules.csr_bridge = wishbone2csr.WB2CSR(
bus_csr = csr_bus.Interface( bus_csr = csr_bus.Interface(
address_width = self.csr.address_width, address_width = self.csr.address_width,
data_width = self.csr.data_width)) data_width = self.csr.data_width))
csr_size = 2**(self.csr.address_width + 2) csr_size = 2**(self.csr.address_width + 2)
csr_region = SoCRegion(origin=origin, size=csr_size, cached=False) csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region) self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region)

27
litex/soc/integration/soc_core.py
View File

@ -61,6 +61,11 @@ class SoCCore(LiteXSoC):
} }
def __init__(self, platform, clk_freq, def __init__(self, platform, clk_freq,
# Bus parameters
bus_standard = "wishbone",
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = 1e6,
# CPU parameters # CPU parameters
cpu_type = "vexriscv", cpu_type = "vexriscv",
cpu_reset_address = None, cpu_reset_address = None,
@ -92,18 +97,15 @@ class SoCCore(LiteXSoC):
with_timer = True, with_timer = True,
# Controller parameters # Controller parameters
with_ctrl = True, with_ctrl = True,
# Wishbone parameters
with_wishbone = True,
wishbone_timeout_cycles = 1e6,
# Others # Others
**kwargs): **kwargs):
# New LiteXSoC class ---------------------------------------------------------------------------- # New LiteXSoC class ----------------------------------------------------------------------------
LiteXSoC.__init__(self, platform, clk_freq, LiteXSoC.__init__(self, platform, clk_freq,
bus_standard = "wishbone", bus_standard = bus_standard,
bus_data_width = 32, bus_data_width = bus_data_width,
bus_address_width = 32, bus_address_width = bus_address_width,
bus_timeout = wishbone_timeout_cycles, bus_timeout = bus_timeout,
bus_reserved_regions = {}, bus_reserved_regions = {},
csr_data_width = csr_data_width, csr_data_width = csr_data_width,
@ -127,9 +129,6 @@ class SoCCore(LiteXSoC):
cpu_reset_address = None if cpu_reset_address == "None" else cpu_reset_address cpu_reset_address = None if cpu_reset_address == "None" else cpu_reset_address
cpu_variant = cpu.check_format_cpu_variant(cpu_variant) cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
if not with_wishbone:
self.mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type self.cpu_type = cpu_type
self.cpu_variant = cpu_variant self.cpu_variant = cpu_variant
self.cpu_cls = cpu_cls self.cpu_cls = cpu_cls
@ -141,9 +140,6 @@ class SoCCore(LiteXSoC):
self.csr_data_width = csr_data_width self.csr_data_width = csr_data_width
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
self.wb_slaves = {} self.wb_slaves = {}
# Modules instances ------------------------------------------------------------------------ # Modules instances ------------------------------------------------------------------------
@ -187,9 +183,8 @@ class SoCCore(LiteXSoC):
if with_timer: if with_timer:
self.add_timer(name="timer0") self.add_timer(name="timer0")
# Add Wishbone to CSR bridge # Add CSR bridge
if with_wishbone: self.add_csr_bridge(self.mem_map["csr"])
self.add_csr_bridge(self.mem_map["csr"])
# Methods -------------------------------------------------------------------------------------- # Methods --------------------------------------------------------------------------------------