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soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.

This commit is contained in:
Florent Kermarrec 2020-05-11 22:39:17 +02:00
parent 1e610600f6
commit e2176cefc2
2 changed files with 13 additions and 18 deletions
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25
litex/soc/integration/soc_core.py
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@ -61,6 +61,11 @@ class SoCCore(LiteXSoC):
}
def __init__(self, platform, clk_freq,
# Bus parameters
bus_standard = "wishbone",
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = 1e6,
# CPU parameters
cpu_type = "vexriscv",
cpu_reset_address = None,
@ -92,18 +97,15 @@ class SoCCore(LiteXSoC):
with_timer = True,
# Controller parameters
with_ctrl = True,
# Wishbone parameters
with_wishbone = True,
wishbone_timeout_cycles = 1e6,
# Others
**kwargs):
# New LiteXSoC class ----------------------------------------------------------------------------
LiteXSoC.__init__(self, platform, clk_freq,
bus_standard = "wishbone",
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = wishbone_timeout_cycles,
bus_standard = bus_standard,
bus_data_width = bus_data_width,
bus_address_width = bus_address_width,
bus_timeout = bus_timeout,
bus_reserved_regions = {},
csr_data_width = csr_data_width,
@ -127,9 +129,6 @@ class SoCCore(LiteXSoC):
cpu_reset_address = None if cpu_reset_address == "None" else cpu_reset_address
cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
if not with_wishbone:
self.mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu_variant
self.cpu_cls = cpu_cls
@ -141,9 +140,6 @@ class SoCCore(LiteXSoC):
self.csr_data_width = csr_data_width
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
self.wb_slaves = {}
# Modules instances ------------------------------------------------------------------------
@ -187,8 +183,7 @@ class SoCCore(LiteXSoC):
if with_timer:
self.add_timer(name="timer0")
# Add Wishbone to CSR bridge
if with_wishbone:
# Add CSR bridge
self.add_csr_bridge(self.mem_map["csr"])
# Methods --------------------------------------------------------------------------------------