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build/vhd2v_converter.py: pass work_package to platform

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Gwenhael Goavec-Merou 2024-06-06 15:24:20 +02:00
parent b2b7130b7b
commit e25de0f499
1 changed files with 2 additions and 1 deletions
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litex/build/vhd2v_converter.py
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@ -61,6 +61,7 @@ class VHD2VConverter(Module):
self._params = params self._params = params
self._force_convert = force_convert self._force_convert = force_convert
self._add_instance = add_instance self._add_instance = add_instance
self._work_package = work_package
self._ghdl_opts = ["--std=08", "--no-formal"] self._ghdl_opts = ["--std=08", "--no-formal"]
@ -103,7 +104,7 @@ class VHD2VConverter(Module):
if self._platform.support_mixed_language and not self._force_convert: if self._platform.support_mixed_language and not self._force_convert:
ip_params = self._params ip_params = self._params
for file in self._sources: for file in self._sources:
self._platform.add_source(file) self._platform.add_source(file, library=self._work_package)
else: # platform is only able to synthesis verilog -> convert vhdl to verilog else: # platform is only able to synthesis verilog -> convert vhdl to verilog
# check if more than one core is instanciated # check if more than one core is instanciated
# if so -> append with _X # if so -> append with _X