platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows)
This commit is contained in:
parent
bbfce2b707
commit
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5
Makefile
5
Makefile
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@ -2,9 +2,10 @@ MSCDIR = ../misoc
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CURDIR = ../k7sataphy
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CURDIR = ../k7sataphy
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PYTHON = python3
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PYTHON = python3
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TOOLCHAIN = ise
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TOOLCHAIN = ise
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PLATFORM = kc705_impact
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PLATFORM = kc705
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PROGRAMMER = impact
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CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -p $(PLATFORM) -t test
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CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -Op programmer $(PROGRAMMER) -p $(PLATFORM) -t test
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csv:
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csv:
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cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv
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cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv
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@ -68,12 +68,12 @@ _io = [
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),
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),
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("sata_host", 0,
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("sata_host", 0,
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Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII
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Subsignal("refclk_p", Pins("C8")),
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Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII
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Subsignal("refclk_n", Pins("C7")),
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Subsignal("txp", Pins("H2")), # SFP
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Subsignal("txp", Pins("D2")),
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Subsignal("txn", Pins("H1")), # SFP
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Subsignal("txn", Pins("D1")),
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Subsignal("rxp", Pins("G4")), # SFP
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Subsignal("rxp", Pins("E4")),
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Subsignal("rxn", Pins("G3")), # SFP
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Subsignal("rxn", Pins("E3")),
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),
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),
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("sata_device", 0,
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("sata_device", 0,
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@ -86,7 +86,7 @@ _io = [
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),
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),
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]
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]
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def Platform(*args, toolchain="vivado", **kwargs):
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def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
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if toolchain == "ise":
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if toolchain == "ise":
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xilinx_platform = XilinxISEPlatform
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado":
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elif toolchain == "vivado":
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@ -101,7 +101,12 @@ def Platform(*args, toolchain="vivado", **kwargs):
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def create_programmer(self):
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def create_programmer(self):
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return IMPACT()
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if programmer == "xc3sprog":
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return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
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elif programmer == "impact":
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return IMPACT()
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else:
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raise ValueError
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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try:
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try:
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@ -111,5 +116,5 @@ def Platform(*args, toolchain="vivado", **kwargs):
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try:
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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except ConstraintError:
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pass
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pass
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return RealPlatform(*args, **kwargs)
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return RealPlatform(*args, **kwargs)
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@ -1,95 +0,0 @@
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from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx_common import CRG_DS
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from mibuild.xilinx_ise import XilinxISEPlatform
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from mibuild.xilinx_vivado import XilinxVivadoPlatform
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from mibuild.programmer import XC3SProg
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")
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),
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("sata_host", 0,
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Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII
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Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII
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Subsignal("txp", Pins("H2")), # SFP
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Subsignal("txn", Pins("H1")), # SFP
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Subsignal("rxp", Pins("G4")), # SFP
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Subsignal("rxn", Pins("G3")), # SFP
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),
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("sata_device", 0,
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Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII
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Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII
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Subsignal("txp", Pins("H2")), # SFP
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Subsignal("txn", Pins("H1")), # SFP
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Subsignal("rxp", Pins("G4")), # SFP
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Subsignal("rxn", Pins("G3")), # SFP
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),
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]
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def Platform(*args, toolchain="vivado", **kwargs):
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if toolchain == "ise":
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado":
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xilinx_platform = XilinxVivadoPlatform
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else:
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raise ValueError
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class RealPlatform(xilinx_platform):
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def create_programmer(self):
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return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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pass
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return RealPlatform(*args, **kwargs)
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@ -89,7 +89,7 @@ class UART2WB(Module):
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class TestDesign(UART2WB):
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class TestDesign(UART2WB):
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default_platform = "kc705"
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default_platform = "kc705"
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def __init__(self, platform):
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def __init__(self, platform, simulation=False):
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clk_freq = 166666*1000
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clk_freq = 166666*1000
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UART2WB.__init__(self, platform, clk_freq)
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform)
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@ -99,10 +99,11 @@ class TestDesign(UART2WB):
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self.sataphy_host.sink.stb.eq(1),
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self.sataphy_host.sink.stb.eq(1),
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self.sataphy_host.sink.payload.d.eq(0x12345678)
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self.sataphy_host.sink.payload.d.eq(0x12345678)
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]
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]
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
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if simulation:
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self.comb += [
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
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self.sataphy_device.sink.stb.eq(1),
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self.comb += [
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self.sataphy_device.sink.payload.d.eq(0x12345678)
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self.sataphy_device.sink.stb.eq(1),
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]
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self.sataphy_device.sink.payload.d.eq(0x12345678)
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]
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default_subtarget = TestDesign
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default_subtarget = TestDesign
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