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Merge pull request #337 from gregdavill/spi-flash 

soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
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enjoy-digital 2020-01-09 13:24:17 +01:00 committed by GitHub
parent 2cf95e9f93 49781467d7
commit e318287ec2
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1 changed files with 6 additions and 1 deletions
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7
litex/soc/cores/spi_flash.py
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@ -8,6 +8,7 @@
from migen import * from migen import *
from migen.genlib.misc import timeline from migen.genlib.misc import timeline
from migen.fhdl.specials import Tristate
from litex.gen import * from litex.gen import *
@ -120,7 +121,11 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
addr_width = 24 addr_width = 24
dq = TSTriple(spi_width) dq = TSTriple(spi_width)
self.specials.dq = dq.get_tristate(pads.dq) # Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
self.specials.dq0 = Tristate(pads.dq[0], o=dq.o[0], i=dq.i[0], oe=dq.oe)
self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe)
self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage))
self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage))
sr = Signal(max(cmd_width, addr_width, wbone_width)) sr = Signal(max(cmd_width, addr_width, wbone_width))
if endianness == "big": if endianness == "big":