Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/cpu/femtorv: Fix typos (thanks @BrunoLevy) and remove TODO (upstream has been updated).

This commit is contained in:
Florent Kermarrec 2021-11-19 22:43:57 +01:00
parent 59d5b1230f
commit e383212ffb
1 changed files with 2 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
litex/soc/cores/cpu/femtorv/core.py
View File

@ -11,15 +11,6 @@ from migen import *
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# TODO:
# - electron: Issue with ADDR_PAD (Similar to the previous issue with quark).
# - intermissum: Issue with ADDR_PAD (Similar to the previous issue with intermissum).
# - intermissum: Connect Interrupt (but should still work in polling mode).
# - gracilis: Issue with ADDR_PAD (Similar to the previous issue with intermissum).
# - gracilis: Connect Interrupt (but should still work in polling mode).
# - petitbateau: Missing NRV_IS_IO_ADDR.
# Variants ----------------------------------------------------------------------------------------- # Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = { CPU_VARIANTS = {
@ -27,7 +18,7 @@ CPU_VARIANTS = {
"quark": "femtorv32_quark", # Quark: Most elementary version of FemtoRV32. "quark": "femtorv32_quark", # Quark: Most elementary version of FemtoRV32.
"tachyon": "femtorv32_tachyon", # Tachyon: Like Quark but supporting higher freq. "tachyon": "femtorv32_tachyon", # Tachyon: Like Quark but supporting higher freq.
"electron": "femtorv32_electron", # Electron: Adds M support. "electron": "femtorv32_electron", # Electron: Adds M support.
"intermissum": "femtorv32_electron", # Intermissum: Adds Interrupt + CSR. "intermissum": "femtorv32_intermissum", # Intermissum: Adds Interrupt + CSR.
"gracilis": "femtorv32_gracilis", # Gracilis: Adds C support. "gracilis": "femtorv32_gracilis", # Gracilis: Adds C support.
"petitbateau": "femtorv32_petitbateau", # PetitBateau: Adds F support. "petitbateau": "femtorv32_petitbateau", # PetitBateau: Adds F support.
} }
@ -48,7 +39,7 @@ GCC_FLAGS = {
"electron": "-march=rv32im -mabi=ilp32", "electron": "-march=rv32im -mabi=ilp32",
"intermissum": "-march=rv32im -mabi=ilp32", "intermissum": "-march=rv32im -mabi=ilp32",
"gracilis": "-march=rv32imc -mabi=ilp32", "gracilis": "-march=rv32imc -mabi=ilp32",
"petitbateau": "-march=rv32imcf -mabi=ilp32", "petitbateau": "-march=rv32imcf -mabi=ilp32f",
} }
# FemtoRV ------------------------------------------------------------------------------------------ # FemtoRV ------------------------------------------------------------------------------------------