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spi_flash: fix bitbang with spi_width=1

This commit is contained in:
Sebastien Bourdeauducq 2016-12-21 10:57:29 +01:00 committed by Tim 'mithro' Ansell
parent b81839bf1a
commit e39c470bbc
1 changed files with 8 additions and 3 deletions
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11
litex/soc/cores/flash/spi_flash.py
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@ -63,8 +63,6 @@ class SpiFlash(Module, AutoCSR):
self.specials.dq = dq.get_tristate(pads.dq) self.specials.dq = dq.get_tristate(pads.dq)
sr = Signal(max(cmd_width, addr_width, wbone_width)) sr = Signal(max(cmd_width, addr_width, wbone_width))
dqs = Replicate(1, spi_width-1)
self.comb += bus.dat_r.eq(sr) self.comb += bus.dat_r.eq(sr)
hw_read_logic = [ hw_read_logic = [
@ -78,7 +76,6 @@ class SpiFlash(Module, AutoCSR):
bitbang_logic = [ bitbang_logic = [
pads.clk.eq(self.bitbang.storage[1]), pads.clk.eq(self.bitbang.storage[1]),
pads.cs_n.eq(self.bitbang.storage[2]), pads.cs_n.eq(self.bitbang.storage[2]),
dq.o.eq(Cat(self.bitbang.storage[0], dqs)),
If(self.bitbang.storage[3], If(self.bitbang.storage[3],
dq.oe.eq(0) dq.oe.eq(0)
).Else( ).Else(
@ -88,6 +85,14 @@ class SpiFlash(Module, AutoCSR):
self.miso.status.eq(dq.i[1]) self.miso.status.eq(dq.i[1])
) )
] ]
if spi_width > 1:
bitbang_logic += [
dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))
]
else:
bitbang_logic += [
dq.o.eq(self.bitbang.storage[0])
]
self.comb += \ self.comb += \
If(self.bitbang_en.storage, If(self.bitbang_en.storage,