soc/SoCBusHandler: Add get_address_width method to get address_width depending bus standard.

This fixes SDCard/SATA build with and AXI/AXI-Lite Bus.

litex/soc/integration/soc.py

@@ -440,6 +440,21 @@ class SoCBusHandler(Module):
             colorer(name, color="underline"),
             colorer("added", color="green")))
 
+    def get_address_width(self, standard):
+        standard_from = self.standard
+        standard_to   = standard
+
+        # AXI or AXI-Lite SoC Bus and Wishbone requested:
+        if standard_from in ["axi", "axi-lite"] and standard_to in ["wishbone"]:
+            address_shift = log2_int(self.data_width//8)
+            return self.address_width - address_shift
+        # Wishbone SoC Bus and AXI, AXI-Lite requested:
+        if standard_from in ["wishbone"] and standard_to in ["axi", "axi-lite"]:
+            address_shift = log2_int(self.data_width//8)
+            return self.address_width + address_shift
+        # Else just return address_width:
+        return self.address_width
+
     # Str ------------------------------------------------------------------------------------------
     def __str__(self):
         r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
@@ -1038,7 +1053,7 @@ class SoC(Module):
                     name             = "SoCDMABusHandler",
                     standard         = "wishbone",
                     data_width       = self.bus.data_width,
-                    address_width    = self.bus.address_width,
+                    address_width    = self.bus.get_address_width(standard="wishbone"),
                     bursting         = self.bus.bursting
                 )
                 dma_bus = wishbone.Interface(data_width=self.bus.data_width)
@@ -1789,7 +1804,7 @@ class LiteXSoC(SoC):
 
         # Block2Mem DMA.
         if "read" in mode:
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
+            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
             self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
             self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
             dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
@@ -1797,7 +1812,7 @@ class LiteXSoC(SoC):
 
         # Mem2Block DMA.
         if "write" in mode:
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
+            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
             self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
             self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
             dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
@@ -1861,7 +1876,7 @@ class LiteXSoC(SoC):
 
         # Sector2Mem DMA.
         if "read" in mode:
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
+            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
             self.submodules.sata_sector2mem = LiteSATASector2MemDMA(
                port       = self.sata_crossbar.get_port(),
                bus        = bus,
@@ -1871,7 +1886,7 @@ class LiteXSoC(SoC):
 
         # Mem2Sector DMA.
         if "write" in mode:
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
+            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
             self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(
                bus        = bus,
                port       = self.sata_crossbar.get_port(),