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build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools

This commit is contained in:
Florent Kermarrec 2018-11-19 12:50:07 +01:00
parent 4c966114f8
commit e3c6bd5846
1 changed files with 7 additions and 6 deletions
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3
litex/build/microsemi/libero_soc.py
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@ -113,8 +113,9 @@ def _build_tcl(platform, sources, build_dir, build_name):
# import timing constraints # import timing constraints
tcl.append("import_files -convert_EDN_to_HDL 0 -sdc {{{}}}".format(build_name + ".sdc")) tcl.append("import_files -convert_EDN_to_HDL 0 -sdc {{{}}}".format(build_name + ".sdc"))
for tool in ["{SYNTHESIZE}", "{PLACEROUTE}", "{VERIFYTIMING}"]:
tcl.append(" ".join(["organize_tool_files", tcl.append(" ".join(["organize_tool_files",
"-tool {VERIFYTIMING}", "-tool " + tool,
"-file impl/constraint/{}.sdc".format(build_name), "-file impl/constraint/{}.sdc".format(build_name),
"-module {}".format(build_name), "-module {}".format(build_name),
"-input_type {constraint}" "-input_type {constraint}"