build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools

litex/build/microsemi/libero_soc.py

@@ -113,8 +113,9 @@ def _build_tcl(platform, sources, build_dir, build_name):
 
     # import timing constraints
     tcl.append("import_files -convert_EDN_to_HDL 0 -sdc {{{}}}".format(build_name + ".sdc"))
+    for tool in ["{SYNTHESIZE}", "{PLACEROUTE}", "{VERIFYTIMING}"]:
         tcl.append(" ".join(["organize_tool_files",
-        "-tool {VERIFYTIMING}",
+            "-tool " + tool,
             "-file impl/constraint/{}.sdc".format(build_name),
             "-module {}".format(build_name),
             "-input_type {constraint}"