soc/cores/interconnect: Switch most of the cores to new Reduce.

litex/soc/cores/code_8b10b.py

@@ -19,11 +19,10 @@ Note: This encoding is *not* used by DVI/HDMI (that uses a *different* 8b/10b
 scheme called TMDS).
 """
 
-from functools import reduce
-from operator import add
-
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.interconnect import stream
 
 # Helpers ------------------------------------------------------------------------------------------
@@ -335,7 +334,7 @@ class Decoder(Module):
         # Basic invalid symbols detection: check that we have 4,5 or 6 ones in the symbol. This does
         # not report all invalid symbols but still allow detecting issues with the link.
         ones = Signal(4, reset_less=True)
-        self.sync += If(self.ce, ones.eq(reduce(add, [self.input[i] for i in range(10)])))
+        self.sync += If(self.ce, ones.eq(Reduce("ADD", [self.input[i] for i in range(10)])))
         self.comb += self.invalid.eq((ones != 4) & (ones != 5) & (ones != 6))
 
 

litex/soc/cores/code_tmds.py

@@ -5,11 +5,10 @@
 # Copyright (c) 2016-2021 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from functools import reduce
-from operator import add
-
 from migen import *
 
+from litex.gen import *
+
 # Helpers ------------------------------------------------------------------------------------------
 
 control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
@@ -30,7 +29,7 @@ class TMDSEncoder(Module):
         d   = Signal(8)
         n1d = Signal(max=9)
         self.sync += [
-            n1d.eq(reduce(add, [self.d[i] for i in range(8)])),
+            n1d.eq(Reduce("ADD", [self.d[i] for i in range(8)])),
             d.eq(self.d)
         ]
 
@@ -51,8 +50,8 @@ class TMDSEncoder(Module):
         n0q_m = Signal(max=9)
         n1q_m = Signal(max=9)
         self.sync += [
-            n0q_m.eq(reduce(add, [~q_m[i] for i in range(8)])),
-            n1q_m.eq(reduce(add, [q_m[i] for i in range(8)])),
+            n0q_m.eq(Reduce("ADD", [~q_m[i] for i in range(8)])),
+            n1q_m.eq(Reduce("ADD", [q_m[i] for i in range(8)])),
             q_m_r.eq(q_m)
         ]
 

litex/soc/cores/ecc.py

@@ -12,11 +12,10 @@ Hamming codes with additional parity (SECDED):
 - Double Error Detection
 """
 
-from functools import reduce
-from operator import xor
-
 from migen import *
 
+from litex.gen import *
+
 # Helpers ------------------------------------------------------------------------------------------
 
 def compute_m_n(k):
@@ -81,8 +80,7 @@ class SECDED:
             self.comb += codeword[p-1].eq(syndrome[i])
 
     def compute_parity(self, codeword, parity):
-        self.comb += parity.eq(reduce(xor,
-            [codeword[i] for i in range(len(codeword))]))
+        self.comb += parity.eq(Reduce("XOR", [codeword[i] for i in range(len(codeword))]))
 
 # ECC Encoder --------------------------------------------------------------------------------------
 

litex/soc/cores/prbs.py

@@ -5,13 +5,12 @@
 # Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from operator import xor, add
-from functools import reduce
-
 from migen import *
 from migen.genlib.misc import WaitTimer
 from migen.genlib.cdc import MultiReg
 
+from litex.gen import *
+
 # Constants ----------------------------------------------------------------------------------------
 
 PRBS_CONFIG_OFF    = 0b00
@@ -31,7 +30,7 @@ class PRBSGenerator(Module):
         curval = [state[i] for i in range(n_state)]
         curval += [0]*(n_out - n_state)
         for i in range(n_out):
-            nv = reduce(xor, [curval[tap] for tap in taps])
+            nv = Reduce("XOR", [curval[tap] for tap in taps])
             curval.insert(0, nv)
             curval.pop()
 
@@ -110,7 +109,7 @@ class PRBSChecker(Module):
         state  = Signal(n_state, reset=1)
         curval = [state[i] for i in range(n_state)]
         for i in reversed(range(n_in)):
-            correctv = reduce(xor, [curval[tap] for tap in taps])
+            correctv = Reduce("XOR", [curval[tap] for tap in taps])
             self.comb += self.errors[i].eq(self.i[i] != correctv)
             curval.insert(0, self.i[i])
             curval.pop()

litex/soc/interconnect/csr_bus.py

@@ -14,14 +14,13 @@ The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing
 the configuration and status registers of cores from software.
 """
 
-from functools import reduce
-from operator import or_
-
 from migen import *
 from migen.genlib.record import *
 from migen.genlib.misc import chooser
 from migen.util.misc import xdir
 
+from litex.gen import *
+
 from litex.soc.interconnect import csr
 from litex.soc.interconnect.csr import CSRStorage
 
@@ -76,9 +75,9 @@ class InterconnectShared(Module):
     def __init__(self, masters, slaves):
         intermediate = Interface.like(masters[0])
         self.comb += [
-            intermediate.adr.eq(reduce(or_, [masters[i].adr for i in range(len(masters))])),
-            intermediate.we.eq(reduce(or_, [masters[i].we for i in range(len(masters))])),
-            intermediate.dat_w.eq(reduce(or_, [masters[i].dat_w for i in range(len(masters))]))
+            intermediate.adr.eq(  Reduce("OR", [masters[i].adr   for i in range(len(masters))])),
+            intermediate.we.eq(   Reduce("OR", [masters[i].we    for i in range(len(masters))])),
+            intermediate.dat_w.eq(Reduce("OR", [masters[i].dat_w for i in range(len(masters))]))
         ]
         for i in range(len(masters)):
             self.comb += masters[i].dat_r.eq(intermediate.dat_r)

litex/soc/interconnect/wishbone.py

@@ -11,14 +11,13 @@
 
 from math import log2
 
-from functools import reduce
-from operator import or_
-
 from migen import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
 from migen.genlib.misc import split, displacer, chooser, WaitTimer
 
+from litex.gen import *
+
 from litex.build.generic_platform import *
 
 from litex.soc.interconnect import csr, csr_bus
@@ -207,13 +206,13 @@ class Decoder(Module):
 
         # generate master ack (resp. err) by ORing all slave acks (resp. errs)
         self.comb += [
-            master.ack.eq(reduce(or_, [slave[1].ack for slave in slaves])),
-            master.err.eq(reduce(or_, [slave[1].err for slave in slaves]))
+            master.ack.eq(Reduce("OR", [slave[1].ack for slave in slaves])),
+            master.err.eq(Reduce("OR", [slave[1].err for slave in slaves]))
         ]
 
         # mux (1-hot) slave data return
         masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
-        self.comb += master.dat_r.eq(reduce(or_, masked))
+        self.comb += master.dat_r.eq(Reduce("OR", masked))
 
 
 class InterconnectShared(Module):