interconnect/wishbone: add separators and move SDRAM/Cache.
This commit is contained in:
Florent Kermarrec
parent
1fddd0e3d3
commit
e404608cf4
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@ -1,5 +1,5 @@
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# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
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# License: BSD
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@ -10,11 +10,12 @@ from migen import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import split, displacer, chooser, WaitTimer
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from migen.genlib.fsm import FSM, NextState
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from litex.soc.interconnect import csr
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from litex.build.generic_platform import *
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from litex.soc.interconnect import csr
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# Wishbone Definition ------------------------------------------------------------------------------
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_layout = [
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("adr", "adr_width", DIR_M_TO_S),
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@ -97,6 +98,26 @@ class Interface(Record):
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r.append(sig.eq(pad))
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return r
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# Wishbone Timeout ---------------------------------------------------------------------------------
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class Timeout(Module):
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def __init__(self, master, cycles):
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self.error = Signal()
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# # #
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timer = WaitTimer(int(cycles))
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self.submodules += timer
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self.comb += [
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timer.wait.eq(master.stb & master.cyc & ~master.ack),
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If(timer.done,
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master.dat_r.eq((2**len(master.dat_w))-1),
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master.ack.eq(1),
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self.error.eq(1)
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)
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]
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# Wishbone Interconnect ----------------------------------------------------------------------------
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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@ -170,24 +191,6 @@ class Decoder(Module):
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self.comb += master.dat_r.eq(reduce(or_, masked))
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class Timeout(Module):
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def __init__(self, master, cycles):
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self.error = Signal()
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# # #
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timer = WaitTimer(int(cycles))
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self.submodules += timer
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self.comb += [
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timer.wait.eq(master.stb & master.cyc & ~master.ack),
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If(timer.done,
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master.dat_r.eq((2**len(master.dat_w))-1),
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master.ack.eq(1),
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self.error.eq(1)
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)
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]
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class InterconnectShared(Module):
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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shared = Interface()
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@ -209,6 +212,7 @@ class Crossbar(Module):
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for column, bus in zip(zip(*access), busses):
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self.submodules += Arbiter(column, bus)
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# Wishbone Data Width Converter --------------------------------------------------------------------
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class DownConverter(Module):
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"""DownConverter
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@ -316,6 +320,49 @@ class Converter(Module):
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else:
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self.comb += master.connect(slave)
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# Wishbone SRAM ------------------------------------------------------------------------------------
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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bus_data_width = len(self.bus.dat_r)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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if read_only is None:
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if hasattr(self.mem, "bus_read_only"):
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read_only = self.mem.bus_read_only
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else:
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read_only = False
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###
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# memory
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port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
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mode=READ_FIRST if read_only else WRITE_FIRST)
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self.specials += self.mem, port
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# generate write enable signal
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if not read_only:
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self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(bus_data_width//8)]
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# address and data
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self.comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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self.bus.dat_r.eq(port.dat_r)
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]
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.dat_w),
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# generate ack
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self.sync += [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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]
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# Wishbone Cache -----------------------------------------------------------------------------------
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class Cache(Module):
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"""Cache
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@ -471,47 +518,7 @@ class Cache(Module):
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)
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)
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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bus_data_width = len(self.bus.dat_r)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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if read_only is None:
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if hasattr(self.mem, "bus_read_only"):
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read_only = self.mem.bus_read_only
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else:
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read_only = False
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###
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# memory
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port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
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mode=READ_FIRST if read_only else WRITE_FIRST)
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self.specials += self.mem, port
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# generate write enable signal
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if not read_only:
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self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(bus_data_width//8)]
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# address and data
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self.comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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self.bus.dat_r.eq(port.dat_r)
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]
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.dat_w),
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# generate ack
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self.sync += [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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]
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# Wishbone CSRBank ---------------------------------------------------------------------------------
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class CSRBank(csr.GenericBank):
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def __init__(self, description, bus=None):
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