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gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign

This commit is contained in:
Florent Kermarrec 2015-11-16 16:18:09 +01:00
parent 2f52d364af
commit e407a1cdda
1 changed files with 8 additions and 8 deletions
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14
litex/gen/fhdl/verilog.py
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@ -234,9 +234,6 @@ def _printcomb(f, ns,
for t in targets: for t in targets:
target_stmt_map[t].append(statement) target_stmt_map[t].append(statement)
#from pprint import pprint
#pprint(target_stmt_map)
groups = group_by_targets(f.comb) groups = group_by_targets(f.comb)
for n, (t, stmts) in enumerate(target_stmt_map.items()): for n, (t, stmts) in enumerate(target_stmt_map.items()):
@ -331,7 +328,10 @@ def _printspecials(overrides, specials, ns, add_data_file):
def convert(f, ios=None, name="top", def convert(f, ios=None, name="top",
special_overrides=dict(), special_overrides=dict(),
create_clock_domains=True, create_clock_domains=True,
display_run=False, asic_syntax=False): display_run=False,
reg_initialization=True,
dummy_signal=True,
blocking_assign=False):
r = ConvOutput() r = ConvOutput()
if not isinstance(f, _Fragment): if not isinstance(f, _Fragment):
f = f.get_fragment() f = f.get_fragment()
@ -363,11 +363,11 @@ def convert(f, ios=None, name="top",
src = "/* Machine-generated using LiteX gen*/\n" src = "/* Machine-generated using LiteX gen*/\n"
src += _printheader(f, ios, name, ns, src += _printheader(f, ios, name, ns,
reg_initialization=not asic_syntax) reg_initialization=reg_initialization)
src += _printcomb(f, ns, src += _printcomb(f, ns,
display_run=display_run, display_run=display_run,
dummy_signal=not asic_syntax, dummy_signal=dummy_signal,
blocking_assign=asic_syntax) blocking_assign=blocking_assign)
src += _printsync(f, ns) src += _printsync(f, ns)
src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file) src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file)
src += "endmodule\n" src += "endmodule\n"