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interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.

This commit is contained in:
Florent Kermarrec 2020-08-14 00:47:05 +02:00
parent b344196aba
commit e4f5dd987e
1 changed files with 36 additions and 17 deletions
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53
litex/soc/interconnect/wishbone.py
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@ -366,7 +366,7 @@ class SRAM(Module):
# Wishbone To CSR ---------------------------------------------------------------------------------- # Wishbone To CSR ----------------------------------------------------------------------------------
class Wishbone2CSR(Module): class Wishbone2CSR(Module):
def __init__(self, bus_wishbone=None, bus_csr=None): def __init__(self, bus_wishbone=None, bus_csr=None, register=True):
self.csr = bus_csr self.csr = bus_csr
if self.csr is None: if self.csr is None:
# If no CSR bus provided, create it with default parameters. # If no CSR bus provided, create it with default parameters.
@ -378,24 +378,43 @@ class Wishbone2CSR(Module):
# # # # # #
self.comb += [ if register:
self.csr.dat_w.eq(self.wishbone.dat_w), fsm = FSM(reset_state="IDLE")
self.wishbone.dat_r.eq(self.csr.dat_r) self.submodules += fsm
] fsm.act("IDLE",
NextValue(self.csr.dat_w, self.wishbone.dat_w),
fsm = FSM(reset_state="WRITE-READ") If(self.wishbone.cyc & self.wishbone.stb,
self.submodules += fsm NextValue(self.csr.adr, self.wishbone.adr),
fsm.act("WRITE-READ", NextValue(self.csr.we, self.wishbone.we & (self.wishbone.sel != 0)),
If(self.wishbone.cyc & self.wishbone.stb, NextState("WRITE-READ")
self.csr.adr.eq(self.wishbone.adr), )
self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)), )
fsm.act("WRITE-READ",
NextValue(self.csr.adr, 0),
NextValue(self.csr.we, 0),
NextState("ACK") NextState("ACK")
) )
) fsm.act("ACK",
fsm.act("ACK", self.wishbone.ack.eq(1),
self.wishbone.ack.eq(1), self.wishbone.dat_r.eq(self.csr.dat_r),
NextState("WRITE-READ") NextState("IDLE")
) )
else:
fsm = FSM(reset_state="WRITE-READ")
self.submodules += fsm
fsm.act("WRITE-READ",
self.csr.dat_w.eq(self.wishbone.dat_w),
If(self.wishbone.cyc & self.wishbone.stb,
self.csr.adr.eq(self.wishbone.adr),
self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
NextState("ACK")
)
)
fsm.act("ACK",
self.wishbone.ack.eq(1),
self.wishbone.dat_r.eq(self.csr.dat_r),
NextState("WRITE-READ")
)
# Wishbone Cache ----------------------------------------------------------------------------------- # Wishbone Cache -----------------------------------------------------------------------------------