Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1804 from zeldin/ecp5_pll_phase 

cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output
This commit is contained in:
enjoy-digital 2023-10-27 11:37:50 +02:00 committed by GitHub
parent 63159aa187 6636560c41
commit e55cf0f6d9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/soc/cores/clock/lattice_ecp5.py
View File

@ -159,11 +159,11 @@ class ECP5PLL(LiteXModule):
self.comb += self.locked.eq(locked & ~self.reset)
for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
div = config[f"clko{n}_div"]
cphase = int(p*(div + 1)/360 + div - 1)
phase = round(p*div/45)
self.params[f"p_CLKO{n_to_l[n]}_ENABLE"] = "ENABLED"
self.params[f"p_CLKO{n_to_l[n]}_DIV"] = div
self.params[f"p_CLKO{n_to_l[n]}_FPHASE"] = 0
self.params[f"p_CLKO{n_to_l[n]}_CPHASE"] = cphase
self.params[f"p_CLKO{n_to_l[n]}_FPHASE"] = phase & 7
self.params[f"p_CLKO{n_to_l[n]}_CPHASE"] = (phase >> 3) + (div - 1)
self.params[f"o_CLKO{n_to_l[n]}"] = clk
if f > 0: # i.e. not a feedback-only clock
self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))