cores/video: Add VideoS6HDMIPHY (using stream.Gearbox for 10:2 convertion).
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@ -674,7 +674,66 @@ class VideoDVIPHY(Module):
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self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
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# HDMI (7-Series).
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# HDMI (Xilinx Spartan6).
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class VideoS6HDMI10to1Serializer(Module):
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def __init__(self, data_i, data_o, clock_domain):
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# Clock Domain Crossing.
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self.submodules.cdc = stream.ClockDomainCrossing([("data", 10)], cd_from=clock_domain, cd_to=clock_domain + "5x")
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self.comb += self.cdc.sink.valid.eq(1)
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self.comb += self.cdc.sink.data.eq(data_i)
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# 10:2 Gearbox.
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self.submodules.gearbox = ClockDomainsRenamer(clock_domain + "5x")(stream.Gearbox(i_dw=10, o_dw=2, msb_first=False))
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self.comb += self.cdc.source.connect(self.gearbox.sink)
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# 2:1 Output DDR.
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self.comb += self.gearbox.source.ready.eq(1)
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self.specials += DDROutput(
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clk = ClockSignal(clock_domain + "5x"),
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i1 = self.gearbox.source.data[0],
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i2 = self.gearbox.source.data[1],
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o = data_o,
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)
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class VideoS6HDMIPHY(Module):
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def __init__(self, pads, clock_domain="sys"):
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self.sink = sink = stream.Endpoint(video_data_layout)
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# # #
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# Always ack Sink, no backpressure.
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self.comb += sink.ready.eq(1)
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# Clocking + Differential Signaling.
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pads_clk = Signal()
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self.specials += DDROutput(i1=1, i2=0, o=pads_clk, clk=ClockSignal(clock_domain))
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self.specials += Instance("OBUFDS", i_I=pads_clk, o_O=pads.clk_p, o_OB=pads.clk_n)
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# Encode/Serialize Datas.
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for color in ["r", "g", "b"]:
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# TMDS Encoding.
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encoder = ClockDomainsRenamer(clock_domain)(TMDSEncoder())
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setattr(self.submodules, f"{color}_encoder", encoder)
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self.comb += encoder.d.eq(getattr(sink, color))
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self.comb += encoder.c.eq(Cat(sink.hsync, sink.vsync) if color == "r" else 0)
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self.comb += encoder.de.eq(sink.de)
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# 10:1 Serialization + Differential Signaling.
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pad_o = Signal()
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serializer = VideoS6HDMI10to1Serializer(
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data_i = encoder.out,
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data_o = pad_o,
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clock_domain = clock_domain,
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)
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setattr(self.submodules, f"{color}_serializer", serializer)
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c2d = {"r": 0, "g": 1, "b": 2}
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pad_p = getattr(pads, f"data{c2d[color]}_p")
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pad_n = getattr(pads, f"data{c2d[color]}_n")
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self.specials += Instance("OBUFDS", i_I=pad_o, o_O=pad_p, o_OB=pad_n)
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# HDMI (Xilinx 7-Series).
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class VideoS7HDMI10to1Serializer(Module):
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class VideoS7HDMI10to1Serializer(Module):
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def __init__(self, data_i, data_o, clock_domain):
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def __init__(self, data_i, data_o, clock_domain):
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