lasmicon: add FIFO at bankmachine input to ease timing
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a04d53be07
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@ -20,7 +20,7 @@ class GeomSettings:
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self.mux_a = max(row_a, col_a)
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self.mux_a = max(row_a, col_a)
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class TimingSettings:
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class TimingSettings:
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def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, CL, read_latency, write_latency, read_time, write_time):
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def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, read_latency, write_latency, req_queue_size, read_time, write_time):
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self.tRP = tRP
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self.tRP = tRP
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self.tRCD = tRCD
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self.tRCD = tRCD
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self.tWR = tWR
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self.tWR = tWR
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@ -28,10 +28,10 @@ class TimingSettings:
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self.tREFI = tREFI
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self.tREFI = tREFI
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self.tRFC = tRFC
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self.tRFC = tRFC
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self.CL = CL
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self.read_latency = read_latency
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self.read_latency = read_latency
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self.write_latency = write_latency
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self.write_latency = write_latency
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self.req_queue_size = req_queue_size
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self.read_time = read_time
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self.read_time = read_time
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self.write_time = write_time
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self.write_time = write_time
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@ -48,6 +48,7 @@ class LASMIcon(Module):
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aw=geom_settings.row_a + geom_settings.col_a - address_align,
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aw=geom_settings.row_a + geom_settings.col_a - address_align,
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dw=phy_settings.dfi_d*phy_settings.nphases,
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dw=phy_settings.dfi_d*phy_settings.nphases,
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nbanks=2**geom_settings.bank_a,
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nbanks=2**geom_settings.bank_a,
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req_queue_size=timing_settings.req_queue_size,
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read_latency=timing_settings.read_latency+1,
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read_latency=timing_settings.read_latency+1,
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write_latency=timing_settings.write_latency+1)
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write_latency=timing_settings.write_latency+1)
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self.nrowbits = geom_settings.col_a - address_align
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self.nrowbits = geom_settings.col_a - address_align
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@ -3,6 +3,7 @@ from migen.bus.asmibus import *
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from migen.genlib.roundrobin import *
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from migen.genlib.roundrobin import *
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from migen.genlib.fsm import FSM
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from migen.genlib.fsm import FSM
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from migen.genlib.misc import optree
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from migen.genlib.misc import optree
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from migen.genlib.fifo import SyncFIFO
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from milkymist.lasmicon.multiplexer import *
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from milkymist.lasmicon.multiplexer import *
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@ -33,19 +34,32 @@ class BankMachine(Module):
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###
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###
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# Request FIFO
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self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size)
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self.comb += [
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self.req_fifo.din.we.eq(req.we),
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self.req_fifo.din.adr.eq(req.adr),
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self.req_fifo.we.eq(req.stb),
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req.req_ack.eq(self.req_fifo.writable),
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self.req_fifo.re.eq(req.dat_ack),
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req.lock.eq(self.req_fifo.readable)
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]
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reqf = self.req_fifo.dout
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slicer = _AddressSlicer(geom_settings.col_a, address_align)
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slicer = _AddressSlicer(geom_settings.col_a, address_align)
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# Row tracking
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# Row tracking
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has_openrow = Signal()
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has_openrow = Signal()
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openrow = Signal(geom_settings.row_a)
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openrow = Signal(geom_settings.row_a)
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hit = Signal()
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hit = Signal()
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self.comb += hit.eq(openrow == slicer.row(req.adr))
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self.comb += hit.eq(openrow == slicer.row(reqf.adr))
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track_open = Signal()
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track_open = Signal()
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track_close = Signal()
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track_close = Signal()
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self.sync += [
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self.sync += [
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If(track_open,
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If(track_open,
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has_openrow.eq(1),
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has_openrow.eq(1),
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openrow.eq(slicer.row(req.adr))
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openrow.eq(slicer.row(reqf.adr))
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),
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),
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If(track_close,
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If(track_close,
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has_openrow.eq(0)
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has_openrow.eq(0)
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@ -57,9 +71,9 @@ class BankMachine(Module):
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self.comb += [
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self.comb += [
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self.cmd.ba.eq(bankn),
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self.cmd.ba.eq(bankn),
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If(s_row_adr,
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If(s_row_adr,
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self.cmd.a.eq(slicer.row(req.adr))
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self.cmd.a.eq(slicer.row(reqf.adr))
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).Else(
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).Else(
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self.cmd.a.eq(slicer.col(req.adr))
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self.cmd.a.eq(slicer.col(reqf.adr))
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)
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)
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]
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]
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@ -85,16 +99,16 @@ class BankMachine(Module):
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fsm.act(fsm.REGULAR,
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fsm.act(fsm.REGULAR,
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If(self.refresh_req,
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If(self.refresh_req,
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fsm.next_state(fsm.REFRESH)
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fsm.next_state(fsm.REFRESH)
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).Elif(req.stb,
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).Elif(self.req_fifo.readable,
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If(has_openrow,
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If(has_openrow,
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If(hit,
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If(hit,
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# NB: write-to-read specification is enforced by multiplexer
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# NB: write-to-read specification is enforced by multiplexer
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self.cmd.stb.eq(1),
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self.cmd.stb.eq(1),
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req.ack.eq(self.cmd.ack),
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req.dat_ack.eq(self.cmd.ack),
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self.cmd.is_read.eq(~req.we),
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self.cmd.is_read.eq(~reqf.we),
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self.cmd.is_write.eq(req.we),
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self.cmd.is_write.eq(reqf.we),
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self.cmd.cas_n.eq(0),
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self.cmd.cas_n.eq(0),
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self.cmd.we_n.eq(~req.we)
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self.cmd.we_n.eq(~reqf.we)
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).Else(
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).Else(
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fsm.next_state(fsm.PRECHARGE)
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fsm.next_state(fsm.PRECHARGE)
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)
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)
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