Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc: add automatic bus data width convertion to add_master/add_slave

This commit is contained in:
Florent Kermarrec 2020-02-07 15:29:54 +01:00
parent 8f67f1157d
commit e5a8ac1dab
2 changed files with 24 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
litex/soc/integration/soc.py
View File

@ -72,7 +72,7 @@ class SoCLinkerRegion(SoCRegion):
# SoCBusHandler ------------------------------------------------------------------------------------
class SoCBusHandler:
class SoCBusHandler(Module):
supported_standard = ["wishbone"]
supported_data_width = [32, 64]
supported_address_width = [32]
@ -215,6 +215,15 @@ class SoCBusHandler:
self.logger.error("{} already declared as Bus Master:".format(colorer(name, color="red")))
self.logger.error(self)
raise
if master.data_width != self.data_width:
self.logger.error("{} Bus Master {} from {}-bit to {}-bit.".format(
colorer(name),
colorer("converted", color="yellow"),
colorer(master.data_width),
colorer(self.data_width)))
new_master = wishbone.Interface(data_width=self.data_width)
self.submodules += wishbone.Converter(master, new_master)
master = new_master
self.masters[name] = master
self.logger.info("{} {} as Bus Master.".format(colorer(name, color="underline"), colorer("added", color="green")))
# FIXME: handle IO regions
@ -240,6 +249,15 @@ class SoCBusHandler:
self.logger.error("{} already declared as Bus Slave:".format(colorer(name, color="red")))
self.logger.error(self)
raise
if slave.data_width != self.data_width:
self.logger.error("{} Bus Slave {} from {}-bit to {}-bit.".format(
colorer(name),
colorer("converted", color="yellow"),
colorer(slave.data_width),
colorer(self.data_width)))
new_slave = wishbone.Interface(data_width=self.data_width)
self.submodules += wishbone.Converter(slave, new_slave)
slave = new_slave
self.slaves[name] = slave
self.logger.info("{} {} as Bus Slave.".format(
colorer(name, color="underline"),
@ -263,7 +281,7 @@ class SoCBusHandler:
# SoCLocHandler --------------------------------------------------------------------------------------
class SoCLocHandler:
class SoCLocHandler(Module):
# Creation -------------------------------------------------------------------------------------
def __init__(self, name, n_locs):
self.name = name
@ -485,7 +503,7 @@ class SoC(Module):
self.logger.info(colorer("-"*80, color="bright"))
# SoC Bus Handler --------------------------------------------------------------------------
self.bus = SoCBusHandler(
self.submodules.bus = SoCBusHandler(
standard = bus_standard,
data_width = bus_data_width,
address_width = bus_address_width,
@ -494,7 +512,7 @@ class SoC(Module):
)
# SoC Bus Handler --------------------------------------------------------------------------
self.csr = SoCCSRHandler(
self.submodules.csr = SoCCSRHandler(
data_width = csr_data_width,
address_width = csr_address_width,
alignment = csr_alignment,
@ -503,7 +521,7 @@ class SoC(Module):
)
# SoC IRQ Handler --------------------------------------------------------------------------
self.irq = SoCIRQHandler(
self.submodules.irq = SoCIRQHandler(
n_irqs = irq_n_irqs,
reserved_irqs = irq_reserved_irqs
)
@ -516,7 +534,6 @@ class SoC(Module):
self.logger.info(self.irq)
self.logger.info(colorer("-"*80, color="bright"))
def do_finalize(self):
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Finalized SoC:", color="cyan"))

5
litex/soc/integration/soc_core.py
View File

@ -162,10 +162,7 @@ class SoCCore(SoC):
# Add CPU buses as 32-bit Wishbone masters
for cpu_bus in self.cpu.buses:
assert cpu_bus.data_width in [32, 64, 128]
soc_bus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules += wishbone.Converter(cpu_bus, soc_bus)
self.add_wb_master(soc_bus)
self.add_wb_master(cpu_bus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", use_loc_if_exists=True)