soc/software: Remove SoCController dependency for BIOS compilation.
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@ -786,7 +786,7 @@ class SoC(Module):
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def check_bios_requirements(self):
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def check_bios_requirements(self):
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# Check for required Peripherals.
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# Check for required Peripherals.
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for periph in ["ctrl", "timer0"]:
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for periph in [ "timer0"]:
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if periph not in self.csr.locs.keys():
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if periph not in self.csr.locs.keys():
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self.logger.error("BIOS needs {} peripheral to be {}.".format(
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self.logger.error("BIOS needs {} peripheral to be {}.".format(
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colorer(periph),
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colorer(periph),
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@ -39,6 +39,7 @@ static unsigned short seed_to_data_16(unsigned short seed, int random)
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return random ? lfsr(16, seed) : seed + 1;
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return random ? lfsr(16, seed) : seed + 1;
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}
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}
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#ifdef CSR_CTRL_BASE
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int memtest_access(unsigned int *addr)
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int memtest_access(unsigned int *addr)
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{
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{
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volatile unsigned int *array = addr;
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volatile unsigned int *array = addr;
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@ -59,6 +60,7 @@ int memtest_access(unsigned int *addr)
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return 0;
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return 0;
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}
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}
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#endif
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int memtest_bus(unsigned int *addr, unsigned long size)
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int memtest_bus(unsigned int *addr, unsigned long size)
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{
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{
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@ -283,8 +285,10 @@ int memtest(unsigned int *addr, unsigned long maxsize)
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print_size(data_size);
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print_size(data_size);
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printf(")...\n");
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printf(")...\n");
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#ifdef CSR_CTRL_BASE
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if (memtest_access(addr))
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if (memtest_access(addr))
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return 0;
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return 0;
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#endif
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bus_errors = memtest_bus(addr, bus_size);
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bus_errors = memtest_bus(addr, bus_size);
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addr_errors = memtest_addr(addr, addr_size, MEMTEST_ADDR_RANDOM);
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addr_errors = memtest_addr(addr, addr_size, MEMTEST_ADDR_RANDOM);
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