adapt migScope to Migen changes
This commit is contained in:
parent
f96a28fc32
commit
e6042c122c
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@ -4,7 +4,7 @@ class Constraints:
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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assert(signal.bv.width == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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assert(signal.nbits == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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i = 0
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i = 0
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for p in pins:
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for p in pins:
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add(signal, p, i, iostandard, extra)
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add(signal, p, i, iostandard, extra)
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@ -102,11 +102,11 @@ def get():
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# Csr Interconnect
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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[
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migIo0.bank.interface,
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migIo0.bank.bus,
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migLa0.trig.bank.interface,
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migLa0.trig.bank.bus,
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migLa0.rec.bank.interface,
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migLa0.rec.bank.bus,
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migLa1.trig.bank.interface,
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migLa1.trig.bank.bus,
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migLa1.rec.bank.interface,
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migLa1.rec.bank.bus,
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])
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])
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comb = []
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comb = []
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@ -117,13 +117,13 @@ def get():
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#
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#
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# Counter
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# Counter
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cnt_gen = Signal(BV(8))
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cnt_gen = Signal(8)
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sync += [
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sync += [
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cnt_gen.eq(cnt_gen+1)
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cnt_gen.eq(cnt_gen+1)
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]
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]
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# Square
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# Square
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square_gen = Signal(BV(8))
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square_gen = Signal(8)
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sync += [
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sync += [
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If(cnt_gen[7],
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If(cnt_gen[7],
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square_gen.eq(255)
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square_gen.eq(255)
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@ -134,13 +134,18 @@ def get():
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus_re = Signal()
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sinus_re = Signal()
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sinus_gen = Signal(BV(8))
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sinus_gen = Signal(8)
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comb +=[sinus_re.eq(1)]
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comb +=[sinus_re.eq(1)]
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sinus_port = MemoryPort(adr=cnt_gen, re=sinus_re, dat_r=sinus_gen)
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sinus_mem = Memory(8, 256, init = sinus)
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sinus_mem = Memory(8, 256, sinus_port, init = sinus)
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sinus_port = sinus_mem.get_port(has_re=True)
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comb += [
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sinus_port.adr.eq(cnt_gen),
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sinus_port.re.eq(sinus_re),
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sinus_gen.eq(sinus_port.dat_r)
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]
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# Signal Selection
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# Signal Selection
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sig_gen = Signal(BV(8))
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sig_gen = Signal(8)
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comb += [
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comb += [
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If(migIo0.o == 0,
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If(migIo0.o == 0,
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sig_gen.eq(cnt_gen)
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sig_gen.eq(cnt_gen)
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@ -154,7 +159,7 @@ def get():
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]
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]
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# Led
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# Led
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led0 = Signal(BV(8))
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led0 = Signal(8)
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comb += [led0.eq(migIo0.o[:8])]
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comb += [led0.eq(migIo0.o[:8])]
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@ -187,7 +192,7 @@ def get():
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cst = Constraints(in_rst_n, cd_in, spi2csr0, led0)
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cst = Constraints(in_rst_n, cd_in, spi2csr0, led0)
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src_verilog, vns = verilog.convert(frag,
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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cst.get_ios(),
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name="de1",
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name="de0_nano",
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clock_domains={
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clock_domains={
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"sys": cd_in
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"sys": cd_in
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},
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},
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@ -4,7 +4,7 @@ class Constraints:
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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assert(signal.bv.width == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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assert(signal.nbits == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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i = 0
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i = 0
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for p in pins:
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for p in pins:
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add(signal, p, i, iostandard, extra)
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add(signal, p, i, iostandard, extra)
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@ -102,11 +102,11 @@ def get():
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# Csr Interconnect
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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[
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migIo0.bank.interface,
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migIo0.bank.bus,
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migLa0.trig.bank.interface,
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migLa0.trig.bank.bus,
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migLa0.rec.bank.interface,
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migLa0.rec.bank.bus,
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migLa1.trig.bank.interface,
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migLa1.trig.bank.bus,
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migLa1.rec.bank.interface,
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migLa1.rec.bank.bus,
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])
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])
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comb = []
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comb = []
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@ -117,13 +117,13 @@ def get():
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#
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#
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# Counter
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# Counter
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cnt_gen = Signal(BV(8))
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cnt_gen = Signal(8)
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sync += [
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sync += [
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cnt_gen.eq(cnt_gen+1)
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cnt_gen.eq(cnt_gen+1)
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]
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]
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# Square
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# Square
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square_gen = Signal(BV(8))
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square_gen = Signal(8)
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sync += [
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sync += [
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If(cnt_gen[7],
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If(cnt_gen[7],
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square_gen.eq(255)
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square_gen.eq(255)
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@ -134,13 +134,18 @@ def get():
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus_re = Signal()
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sinus_re = Signal()
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sinus_gen = Signal(BV(8))
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sinus_gen = Signal(8)
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comb +=[sinus_re.eq(1)]
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comb +=[sinus_re.eq(1)]
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sinus_port = MemoryPort(adr=cnt_gen, re=sinus_re, dat_r=sinus_gen)
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sinus_mem = Memory(8, 256, init = sinus)
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sinus_mem = Memory(8, 256, sinus_port, init = sinus)
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sinus_port = sinus_mem.get_port(has_re=True)
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comb += [
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sinus_port.adr.eq(cnt_gen),
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sinus_port.re.eq(sinus_re),
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sinus_gen.eq(sinus_port.dat_r)
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]
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# Signal Selection
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# Signal Selection
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sig_gen = Signal(BV(8))
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sig_gen = Signal(8)
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comb += [
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comb += [
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If(migIo0.o == 0,
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If(migIo0.o == 0,
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sig_gen.eq(cnt_gen)
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sig_gen.eq(cnt_gen)
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@ -154,11 +159,11 @@ def get():
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]
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]
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# Led
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# Led
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led0 = Signal(BV(8))
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led0 = Signal(8)
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comb += [led0.eq(migIo0.o[:8])]
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comb += [led0.eq(migIo0.o[:8])]
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#Switch
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#Switch
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sw0 = Signal(BV(8))
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sw0 = Signal(8)
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comb += [migIo0.i.eq(sw0)]
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comb += [migIo0.i.eq(sw0)]
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# MigLa0 input
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# MigLa0 input
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@ -15,11 +15,11 @@ class MigIo:
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self.interface = interface
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self.interface = interface
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self.words = int(2**bits_for(width-1)/8)
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self.words = int(2**bits_for(width-1)/8)
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if "I" in self.mode:
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if "I" in self.mode:
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self.i = Signal(BV(self.width))
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self.i = Signal(self.width)
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self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
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self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
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self.ireg.field.w.name_override = "inputs"
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self.ireg.field.w.name_override = "inputs"
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if "O" in self.mode:
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if "O" in self.mode:
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self.o = Signal(BV(self.width))
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self.o = Signal(self.width)
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self.oreg = description.RegisterField("o", self.width)
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self.oreg = description.RegisterField("o", self.width)
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self.oreg.field.r.name_override = "ouptuts"
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self.oreg.field.r.name_override = "ouptuts"
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self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
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self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
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@ -15,8 +15,8 @@ class MigLa:
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self.rec = rec
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self.rec = rec
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self.interface = interface
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self.interface = interface
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self.in_trig = Signal(BV(self.trig.trig_width))
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self.in_trig = Signal(self.trig.trig_width)
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self.in_dat = Signal(BV(self.trig.trig_width))
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self.in_dat = Signal(self.trig.trig_width)
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self.trig.set_address(self.address)
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self.trig.set_address(self.address)
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self.rec.set_address(self.address + 0x0200)
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self.rec.set_address(self.address + 0x0200)
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@ -15,30 +15,43 @@ class Storage:
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#Control
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#Control
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self.rst = Signal()
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self.rst = Signal()
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self.start = Signal()
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self.start = Signal()
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self.offset = Signal(BV(self.depth_width))
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self.offset = Signal(self.depth_width)
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self.size = Signal(BV(self.depth_width))
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self.size = Signal(self.depth_width)
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self.done = Signal()
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self.done = Signal()
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self.run = Signal()
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self.run = Signal()
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#Others
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self._mem = Memory(self.width, self.depth)
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#Write Path
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#Write Path
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self.put = Signal()
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self.put = Signal()
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self.put_dat = Signal(BV(self.width))
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self.put_dat = Signal(self.width)
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self._put_ptr = Signal(BV(self.depth_width))
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self._put_ptr = Signal(self.depth_width)
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self._put_ptr_stop = Signal(BV(self.depth_width))
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self._put_ptr_stop = Signal(self.depth_width)
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self._put_port = MemoryPort(adr=self._put_ptr, we=self.put, dat_w=self.put_dat)
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self._put_port = self._mem.get_port(write_capable=True)
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#Read Path
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#Read Path
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self.get = Signal()
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self.get = Signal()
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self.get_dat = Signal(BV(self.width))
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self.get_dat = Signal(self.width)
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self._get_ptr = Signal(BV(self.depth_width))
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self._get_ptr = Signal(self.depth_width)
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self._get_port = MemoryPort(adr=self._get_ptr, re=self.get, dat_r=self.get_dat)
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self._get_port = self._mem.get_port(has_re=True)
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#Others
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self._mem = Memory(self.width, self.depth, self._put_port, self._get_port)
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def get_fragment(self):
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def get_fragment(self):
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comb = []
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comb = []
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sync = []
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sync = []
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memories = [self._mem]
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memories = [self._mem]
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size_minus_offset = Signal(BV(self.depth_width))
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comb += [
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self._get_port.adr.eq(self._get_ptr),
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self._get_port.re.eq(self.get),
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self.get_dat.eq(self._get_port.dat_r),
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self._put_port.adr.eq(self._put_ptr),
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self._put_port.we.eq(self.put),
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self._put_port.dat_w.eq(self.put_dat)
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]
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size_minus_offset = Signal(self.depth_width)
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comb += [size_minus_offset.eq(self.size-self.offset)]
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comb += [size_minus_offset.eq(self.size-self.offset)]
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#Control
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#Control
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@ -82,8 +95,8 @@ class Sequencer:
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self.depth_width = bits_for(self.depth)
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self.depth_width = bits_for(self.depth)
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# Controller interface
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# Controller interface
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self.ctl_rst = Signal()
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self.ctl_rst = Signal()
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self.ctl_offset = Signal(BV(self.depth_width))
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self.ctl_offset = Signal(self.depth_width)
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self.ctl_size = Signal(BV(self.depth_width))
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self.ctl_size = Signal(self.depth_width)
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self.ctl_arm = Signal()
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self.ctl_arm = Signal()
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self.ctl_done = Signal()
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self.ctl_done = Signal()
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self._ctl_arm_d = Signal()
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self._ctl_arm_d = Signal()
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@ -91,8 +104,8 @@ class Sequencer:
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self.trig_hit = Signal()
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self.trig_hit = Signal()
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self._trig_hit_d = Signal()
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self._trig_hit_d = Signal()
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# Recorder interface
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# Recorder interface
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self.rec_offset = Signal(BV(self.depth_width))
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self.rec_offset = Signal(self.depth_width)
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self.rec_size = Signal(BV(self.depth_width))
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self.rec_size = Signal(self.depth_width)
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self.rec_start = Signal()
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self.rec_start = Signal()
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self.rec_done = Signal()
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self.rec_done = Signal()
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# Others
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# Others
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@ -154,7 +167,7 @@ class Recorder:
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# Trigger Interface
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# Trigger Interface
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self.trig_hit = Signal()
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self.trig_hit = Signal()
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self.trig_dat = Signal(BV(self.width))
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self.trig_dat = Signal(self.width)
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def set_address(self, address):
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def set_address(self, address):
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self.address = address
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self.address = address
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@ -18,9 +18,9 @@ class Term:
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self.reg_size = 2*width
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self.reg_size = 2*width
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self.words = int(2**bits_for(width-1)/8)
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self.words = int(2**bits_for(width-1)/8)
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self.i = Signal(BV(self.width))
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self.i = Signal(self.width)
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self.t = Signal(BV(self.width))
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self.t = Signal(self.width)
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self.m = Signal(BV(self.width))
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self.m = Signal(self.width)
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self.o = Signal()
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self.o = Signal()
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def get_fragment(self):
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def get_fragment(self):
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@ -60,9 +60,9 @@ class RangeDetector:
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self.reg_size = 2*width
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self.reg_size = 2*width
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self.words = int(2**bits_for(width-1)/8)
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self.words = int(2**bits_for(width-1)/8)
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self.i = Signal(BV(self.width))
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self.i = Signal(self.width)
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self.low = Signal(BV(self.width))
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self.low = Signal(self.width)
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self.high = Signal(BV(self.width))
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self.high = Signal(self.width)
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self.o = Signal()
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self.o = Signal()
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def get_fragment(self):
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def get_fragment(self):
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@ -102,16 +102,16 @@ class EdgeDetector:
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self.reg_base = 0
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self.reg_base = 0
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self.reg_size = len(self.mode)*width
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self.reg_size = len(self.mode)*width
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self.i = Signal(BV(self.width))
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self.i = Signal(self.width)
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self.i_d = Signal(BV(self.width))
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self.i_d = Signal(self.width)
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if "R" in self.mode:
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if "R" in self.mode:
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self.r_mask = Signal(BV(self.width))
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self.r_mask = Signal(self.width)
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self.ro = Signal()
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self.ro = Signal()
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if "F" in self.mode:
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if "F" in self.mode:
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self.f_mask = Signal(BV(self.width))
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self.f_mask = Signal(self.width)
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self.fo = Signal()
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self.fo = Signal()
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if "B" in self.mode:
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if "B" in self.mode:
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self.b_mask = Signal(BV(self.width))
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self.b_mask = Signal(self.width)
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||||||
self.bo = Signal()
|
self.bo = Signal()
|
||||||
self.o = Signal()
|
self.o = Signal()
|
||||||
|
|
||||||
|
@ -206,8 +206,8 @@ class Timer:
|
||||||
self.clear = Signal()
|
self.clear = Signal()
|
||||||
|
|
||||||
self.enable = Signal()
|
self.enable = Signal()
|
||||||
self.cnt = Signal(BV(self.width))
|
self.cnt = Signal(self.width)
|
||||||
self.cnt_max = Signal(BV(self.width))
|
self.cnt_max = Signal(self.width)
|
||||||
|
|
||||||
self.o = Signal()
|
self.o = Signal()
|
||||||
|
|
||||||
|
@ -253,26 +253,37 @@ class Sum:
|
||||||
self.pipe = pipe
|
self.pipe = pipe
|
||||||
self.interface = None
|
self.interface = None
|
||||||
|
|
||||||
self.i = Signal(BV(self.width))
|
self._mem = Memory(1, 2**self.width)
|
||||||
|
|
||||||
|
self.i = Signal(self.width)
|
||||||
self._o = Signal()
|
self._o = Signal()
|
||||||
self.o = Signal()
|
self.o = Signal()
|
||||||
self._lut_port = MemoryPort(adr=self.i, dat_r=self._o)
|
self._lut_port = self._mem.get_port()
|
||||||
|
|
||||||
self.reg_name = "sum_reg"
|
self.reg_name = "sum_reg"
|
||||||
self.reg_base = 0
|
self.reg_base = 0
|
||||||
self.reg_size = 32
|
self.reg_size = 32
|
||||||
|
|
||||||
self.prog = Signal()
|
self.prog = Signal()
|
||||||
self.prog_adr = Signal(BV(width))
|
self.prog_adr = Signal(width)
|
||||||
self.prog_dat = Signal()
|
self.prog_dat = Signal()
|
||||||
self._prog_port = MemoryPort(adr=self.prog_adr, we=self.prog, dat_w=self.prog_dat)
|
self._prog_port = self._mem.get_port(write_capable=True)
|
||||||
|
|
||||||
self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port)
|
|
||||||
|
|
||||||
def get_fragment(self):
|
def get_fragment(self):
|
||||||
comb = []
|
comb = []
|
||||||
sync = []
|
sync = []
|
||||||
memories = [self._mem]
|
memories = [self._mem]
|
||||||
|
comb += [
|
||||||
|
self._lut_port.adr.eq(self.i),
|
||||||
|
self._o.eq(self._lut_port.dat_r),
|
||||||
|
|
||||||
|
self._prog_port.adr.eq(self.prog_adr),
|
||||||
|
self._prog_port.we.eq(self.prog),
|
||||||
|
self._prog_port.dat_w.eq(self.prog_dat)
|
||||||
|
]
|
||||||
|
|
||||||
|
|
||||||
if self.pipe:
|
if self.pipe:
|
||||||
sync += [self.o.eq(self._o)]
|
sync += [self.o.eq(self._o)]
|
||||||
else:
|
else:
|
||||||
|
@ -311,7 +322,7 @@ class Trigger:
|
||||||
self.interface = interface
|
self.interface = interface
|
||||||
self.sum = Sum(len(self.ports))
|
self.sum = Sum(len(self.ports))
|
||||||
|
|
||||||
self.in_trig = Signal(BV(self.trig_width))
|
self.in_trig = Signal(self.trig_width)
|
||||||
|
|
||||||
self.hit = Signal()
|
self.hit = Signal()
|
||||||
|
|
||||||
|
|
|
@ -125,7 +125,7 @@ def main():
|
||||||
recorder0.bank.interface
|
recorder0.bank.interface
|
||||||
])
|
])
|
||||||
|
|
||||||
trig_sig = Signal(BV(32))
|
trig_sig = Signal(32)
|
||||||
comb = []
|
comb = []
|
||||||
comb +=[
|
comb +=[
|
||||||
trigger0.in_trig.eq(trig_sig)
|
trigger0.in_trig.eq(trig_sig)
|
||||||
|
|
|
@ -68,10 +68,10 @@ class Spi2Csr :
|
||||||
#
|
#
|
||||||
# Spi --> Csr
|
# Spi --> Csr
|
||||||
#
|
#
|
||||||
spi_cnt = Signal(BV(bits_for(self.a_width+self.max_burst*self.d_width)))
|
spi_cnt = Signal(bits_for(self.a_width+self.max_burst*self.d_width))
|
||||||
spi_addr = Signal(BV(self.a_width))
|
spi_addr = Signal(self.a_width)
|
||||||
spi_w_dat = Signal(BV(self.d_width))
|
spi_w_dat = Signal(self.d_width)
|
||||||
spi_r_dat = Signal(BV(self.d_width))
|
spi_r_dat = Signal(self.d_width)
|
||||||
spi_we = Signal()
|
spi_we = Signal()
|
||||||
spi_re = Signal()
|
spi_re = Signal()
|
||||||
spi_we_re_done = Signal(reset = 1)
|
spi_we_re_done = Signal(reset = 1)
|
||||||
|
@ -126,7 +126,7 @@ class Spi2Csr :
|
||||||
#
|
#
|
||||||
# Csr --> Spi
|
# Csr --> Spi
|
||||||
#
|
#
|
||||||
spi_r_dat_shift = Signal(BV(self.d_width))
|
spi_r_dat_shift = Signal(self.d_width)
|
||||||
sync +=[
|
sync +=[
|
||||||
If(spi_re,
|
If(spi_re,
|
||||||
spi_r_dat_shift.eq(spi_r_dat)
|
spi_r_dat_shift.eq(spi_r_dat)
|
||||||
|
|
Loading…
Reference in New Issue