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board/targets/sim: add identifier

This commit is contained in:
Florent Kermarrec 2017-06-28 18:08:37 +02:00
parent 4433e2449a
commit e61d9eabc6
1 changed files with 1 additions and 0 deletions
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litex/boards/targets/sim.py
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@ -28,6 +28,7 @@ class BaseSoC(SoCSDRAM):
SoCSDRAM.__init__(self, platform, SoCSDRAM.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000), clk_freq=int((1/(platform.default_clk_period))*1000000000),
integrated_rom_size=0x8000, integrated_rom_size=0x8000,
ident="LiteX simulation example design",
with_uart=False, with_uart=False,
**kwargs) **kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.crg = CRG(platform.request(platform.default_clk_name))