board/targets/sim: add identifier

2017-06-28 18:08:37 +02:00 · 2017-06-28 18:08:37 +02:00 · e61d9eabc6
parent 4433e2449a
commit e61d9eabc6
1 changed files with 1 additions and 0 deletions
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@ -28,6 +28,7 @@ class BaseSoC(SoCSDRAM):
        SoCSDRAM.__init__(self, platform,
            clk_freq=int((1/(platform.default_clk_period))*1000000000),
            integrated_rom_size=0x8000,
+            ident="LiteX simulation example design",
            with_uart=False,
            **kwargs)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))