Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support"
This reverts commit0ea6dd91aa, reversing changes made tofa47c62b6d.
This commit is contained in:
Dolu1990
parent
0ea6dd91aa
commit
e62d84b77b
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@ -59,8 +59,6 @@ class VexiiRiscv(CPU):
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with_axi3 = False
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jtag_tap = False
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jtag_instruction = False
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with_cpu_clk = False
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vexii_video = []
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vexii_args = ""
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@ -133,14 +131,12 @@ class VexiiRiscv(CPU):
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cpu_group.add_argument("--with-jtag-instruction", action="store_true", help="Add a JTAG instruction port which implement tunneling for debugging (TAP not included).")
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cpu_group.add_argument("--update-repo", default="recommended", choices=["latest","wipe+latest","recommended","wipe+recommended","no"], help="Specify how the VexiiRiscv & SpinalHDL repo should be updated (latest: update to HEAD, recommended: Update to known compatible version, no: Don't update, wipe+*: Do clean&reset before checkout)")
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cpu_group.add_argument("--no-netlist-cache", action="store_true", help="Always (re-)build the netlist.")
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cpu_group.add_argument("--with-cpu-clk", action="store_true", help="The CPUs will use a decoupled clock")
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# cpu_group.add_argument("--with-fpu", action="store_true", help="Enable the F32/F64 FPU.")
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# cpu_group.add_argument("--with-rvc", action="store_true", help="Enable the Compress ISA extension.")
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cpu_group.add_argument("--l2-bytes", default=0, help="VexiiRiscv L2 bytes, default 128 KB.")
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cpu_group.add_argument("--l2-ways", default=0, help="VexiiRiscv L2 ways, default 8.")
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cpu_group.add_argument("--l2-self-flush", default=None, help="VexiiRiscv L2 ways will self flush on from,to,cycles")
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cpu_group.add_argument("--with-axi3", action="store_true", help="mbus will be axi3 instead of axi4")
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cpu_group.add_argument("--vexii-video", action="append", default=[], help="Add the memory coherent video controller")
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@ -152,7 +148,7 @@ class VexiiRiscv(CPU):
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "a15ea92c", args.update_repo)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "36dad634", args.update_repo)
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if not args.cpu_variant:
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args.cpu_variant = "standard"
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@ -200,12 +196,10 @@ class VexiiRiscv(CPU):
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VexiiRiscv.cpu_count = args.cpu_count
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if args.l2_bytes:
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VexiiRiscv.l2_bytes = args.l2_bytes
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VexiiRiscv.with_cpu_clk = args.with_cpu_clk
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if args.l2_ways:
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VexiiRiscv.l2_ways = args.l2_ways
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if args.l2_self_flush:
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VexiiRiscv.l2_self_flush = args.l2_self_flush
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VexiiRiscv.vexii_video = args.vexii_video
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def __init__(self, platform, variant):
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@ -226,8 +220,8 @@ class VexiiRiscv(CPU):
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# CPU Instance.
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self.cpu_params = dict(
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# Clk/Rst.
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i_litex_clk = ClockSignal("sys"),
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i_litex_reset = ResetSignal("sys") | self.reset,
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i_system_clk = ClockSignal("sys"),
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i_system_reset = ResetSignal("sys") | self.reset,
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# Patcher/Tracer.
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# o_patcher_tracer_valid = self.tracer_valid,
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@ -258,12 +252,6 @@ class VexiiRiscv(CPU):
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i_pBus_rresp = pbus.r.resp,
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)
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if VexiiRiscv.with_cpu_clk:
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self.cpu_clk = Signal()
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self.cpu_params.update(
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i_cpu_clk = self.cpu_clk
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)
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if VexiiRiscv.with_dma:
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self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.internal_bus_width, address_width=32, id_width=4)
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@ -318,31 +306,6 @@ class VexiiRiscv(CPU):
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o_dma_bus_rlast = dma_bus.r.last,
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)
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for video in VexiiRiscv.vexii_video:
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args = {}
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for i, val in enumerate(video.split(",")):
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name, value = val.split("=")
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args.update({name: value})
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name = args["name"]
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clk = Signal()
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hsync = Signal()
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vsync = Signal()
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color_en = Signal()
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color = Signal(16)
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setattr(self, name + "_clk", clk)
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setattr(self, name + "_hsync", hsync)
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setattr(self, name + "_vsync", vsync)
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setattr(self, name + "_color_en", color_en)
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setattr(self, name + "_color", color)
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self.cpu_params["o_" + name + "_clk"] = clk
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self.cpu_params["o_" + name + "_hSync"] = hsync
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self.cpu_params["o_" + name + "_vSync"] = vsync
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self.cpu_params["o_" + name + "_colorEn"] = color_en
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self.cpu_params["o_" + name + "_color"] = color
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def set_reset_address(self, reset_address):
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VexiiRiscv.reset_address = reset_address
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VexiiRiscv.vexii_args += f" --reset-vector {reset_address}"
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@ -356,7 +319,6 @@ class VexiiRiscv(CPU):
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md5_hash.update(str(VexiiRiscv.xlen).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.cpu_count).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_bytes).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.with_cpu_clk).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_ways).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_self_flush).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.jtag_tap).encode('utf-8'))
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@ -365,8 +327,6 @@ class VexiiRiscv(CPU):
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md5_hash.update(str(VexiiRiscv.with_axi3).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8'))
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# md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8'))
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@ -386,8 +346,6 @@ class VexiiRiscv(CPU):
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gen_args.append(VexiiRiscv.vexii_args)
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gen_args.append(f"--cpu-count={VexiiRiscv.cpu_count}")
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gen_args.append(f"--l2-bytes={VexiiRiscv.l2_bytes}")
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if VexiiRiscv.with_cpu_clk:
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gen_args.append("--with-cpu-clk")
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gen_args.append(f"--l2-ways={VexiiRiscv.l2_ways}")
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if VexiiRiscv.l2_self_flush:
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gen_args.append(f"--l2-self-flush={VexiiRiscv.l2_self_flush}")
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@ -403,9 +361,6 @@ class VexiiRiscv(CPU):
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gen_args.append(f"--with-dma")
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if(VexiiRiscv.with_axi3) :
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gen_args.append(f"--with-axi3")
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for arg in VexiiRiscv.vexii_video:
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gen_args.append(f"--video {arg}")
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cmd = f"""cd {ndir} && sbt "runMain vexiiriscv.soc.litex.SocGen {" ".join(gen_args)}\""""
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print("VexiiRiscv generation command :")
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@ -514,12 +469,7 @@ class VexiiRiscv(CPU):
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if soc.get_build_name() == "sim":
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self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1))
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else:
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if hasattr(soc.crg.pll, "locked"):
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self.comb += If(debug_ndmreset, soc.crg.pll.locked.eq(0))
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elif hasattr(soc.crg, "rst"):
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self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
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else:
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raise Exception("Pll has no reset ?")
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self.soc_bus = soc.bus # FIXME: Save SoC Bus instance to retrieve the final mem layout on finalization.
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@ -532,7 +482,6 @@ class VexiiRiscv(CPU):
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id_width = 8,
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version = "axi3" if VexiiRiscv.with_axi3 else "axi4"
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)
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self.mBus_awallStrb = Signal()
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self.memory_buses.append(mbus)
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self.comb += mbus.aw.cache.eq(0xF)
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@ -558,7 +507,7 @@ class VexiiRiscv(CPU):
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o_mBus_awlen = mbus.aw.len,
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o_mBus_awsize = mbus.aw.size,
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o_mBus_awburst = mbus.aw.burst,
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o_mBus_awallStrb = self.mBus_awallStrb,
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o_mBus_awallStrb = Open(),
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# W Channel.
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o_mBus_wvalid = mbus.w.valid,
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i_mBus_wready = mbus.w.ready,
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@ -624,10 +573,6 @@ class VexiiRiscv(CPU):
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mode += "c" if region.cached else ""
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VexiiRiscv.memory_regions.append( (region.origin, region.size, mode, bus) )
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from litex.build.efinix import EfinixPlatform
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if isinstance(self.platform, EfinixPlatform):
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VexiiRiscv.vexii_args = "--mmu-sync-read " + VexiiRiscv.vexii_args
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self.generate_netlist_name()
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# Do verilog instance.
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