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cpu/rocket: bios support for SMP

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This commit is contained in:
Gabriel Somlo 2021-09-19 17:51:50 -04:00
parent 2bc8124114
commit e6aaa40d2d
2 changed files with 46 additions and 0 deletions
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14
litex/soc/cores/cpu/rocket/boot-helper.S
View file

@ -1,4 +1,18 @@
.section .text, "ax", @progbits
.global boot_helper
.global smp_ap_args
.global smp_ap_target
.global smp_ap_ready
boot_helper:
// boot core saves args and jump target for ap cores:
sd a0, smp_ap_args, t1
sd a1, smp_ap_args+8, t1
sd a2, smp_ap_args+16, t1
sd a3, smp_ap_target, t1
fence w, w
// notify application cores to proceed with boot:
li t0, 1
sd t0, smp_ap_ready, t1
// boot core now also ready to boot:
jr a3

32
litex/soc/cores/cpu/rocket/crt0.S
View file

@ -2,6 +2,10 @@
.global isr
.global _start
.global smp_ap_args
.global smp_ap_target
.global smp_ap_ready
_start:
j crt_init
nop
@ -54,9 +58,27 @@ trap_entry:
crt_init:
la sp, _fstack
sd zero, smp_ap_ready, t0
la t0, trap_entry
csrw mtvec, t0
smp_select_bp:
csrr a0, mhartid
beqz a0, data_init // hart 0 is bp, everyone else is ap
smp_ap_loop:
ld t0, smp_ap_ready
beqz t0, smp_ap_loop
smp_ap_boot:
fence r, r
fence.i // i$ flush
ld a0, smp_ap_args // hart ID (but next-stage loads its own)
ld a1, smp_ap_args+8 // DTB pointer (if provded by litex bios)
ld a2, smp_ap_args+16
ld a3, smp_ap_target
jr a3
smp_ap_done:
data_init:
la t0, _fdata
la t1, _edata
@ -88,3 +110,13 @@ bss_done:
call main
inf_loop:
j inf_loop
.bss
smp_ap_args:
.dword 0
.dword 0
.dword 0
smp_ap_target:
.dword 0
smp_ap_ready:
.dword 0