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cpu/rocket: bios support for SMP
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2 changed files with 46 additions and 0 deletions
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@ -1,4 +1,18 @@
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.section .text, "ax", @progbits
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.section .text, "ax", @progbits
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.global boot_helper
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.global boot_helper
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.global smp_ap_args
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.global smp_ap_target
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.global smp_ap_ready
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boot_helper:
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boot_helper:
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// boot core saves args and jump target for ap cores:
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sd a0, smp_ap_args, t1
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sd a1, smp_ap_args+8, t1
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sd a2, smp_ap_args+16, t1
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sd a3, smp_ap_target, t1
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fence w, w
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// notify application cores to proceed with boot:
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li t0, 1
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sd t0, smp_ap_ready, t1
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// boot core now also ready to boot:
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jr a3
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jr a3
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@ -2,6 +2,10 @@
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.global isr
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.global isr
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.global _start
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.global _start
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.global smp_ap_args
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.global smp_ap_target
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.global smp_ap_ready
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_start:
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_start:
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j crt_init
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j crt_init
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nop
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nop
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@ -54,9 +58,27 @@ trap_entry:
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crt_init:
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crt_init:
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la sp, _fstack
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la sp, _fstack
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sd zero, smp_ap_ready, t0
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la t0, trap_entry
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la t0, trap_entry
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csrw mtvec, t0
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csrw mtvec, t0
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smp_select_bp:
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csrr a0, mhartid
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beqz a0, data_init // hart 0 is bp, everyone else is ap
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smp_ap_loop:
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ld t0, smp_ap_ready
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beqz t0, smp_ap_loop
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smp_ap_boot:
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fence r, r
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fence.i // i$ flush
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ld a0, smp_ap_args // hart ID (but next-stage loads its own)
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ld a1, smp_ap_args+8 // DTB pointer (if provded by litex bios)
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ld a2, smp_ap_args+16
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ld a3, smp_ap_target
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jr a3
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smp_ap_done:
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data_init:
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data_init:
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la t0, _fdata
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la t0, _fdata
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la t1, _edata
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la t1, _edata
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@ -88,3 +110,13 @@ bss_done:
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call main
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call main
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inf_loop:
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inf_loop:
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j inf_loop
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j inf_loop
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.bss
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smp_ap_args:
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.dword 0
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.dword 0
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.dword 0
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smp_ap_target:
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.dword 0
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smp_ap_ready:
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.dword 0
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