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soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file)

This commit is contained in:
Florent Kermarrec 2017-12-26 18:11:47 +01:00
parent a3390bb403
commit e7015e4191
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc_core.py
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@ -66,7 +66,7 @@ class SoCCore(Module):
integrated_main_ram_size=0, integrated_main_ram_init=[],
shadow_base=0x80000000,
csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200, uart_stub=False,
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
ident="", ident_version=False,
reserve_nmi_interrupt=True,
with_timer=True):
@ -140,7 +140,7 @@ class SoCCore(Module):
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
else:
del self.soc_interrupt_map["uart"]