tools/litex_gen: Rename to litex_periph_gen to make it more explicit (And also to prepare for litex_soc_gen).
This commit is contained in:
Florent Kermarrec
parent
36ea82546f
commit
e7cee80670
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#!/usr/bin/env python3
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from litex.build.generic_platform import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import axi
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from litex.soc.cores.pwm import PWM
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.cores.spi import SPIMaster, SPISlave
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from litex.soc.cores.clock import S7MMCM
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# Platform -----------------------------------------------------------------------------------------
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_io = [
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("sys_clk", 0, Pins(1)),
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("sys_rst", 0, Pins(1)),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GenericPlatform):
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def __init__(self, io):
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GenericPlatform.__init__(self, "", io)
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def build(self, fragment, build_dir, **kwargs):
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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top_output = self.get_verilog(fragment)
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top_output.write("litex_core.v")
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# LiteXCore ----------------------------------------------------------------------------------------
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class LiteXCore(SoCMini):
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SoCMini.mem_map["csr"] = 0x00000000
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def __init__(self, sys_clk_freq=int(100e6),
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with_pwm = False,
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with_mmcm = False,
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with_gpio = False, gpio_width=32,
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with_spi_master = False, spi_master_data_width=8, spi_master_clk_freq=8e6,
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**kwargs):
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platform = Platform(_io)
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# UART
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if kwargs["with_uart"]:
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platform.add_extension([
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("serial", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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)
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])
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))
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# SoCMini ----------------------------------------------------------------------------------
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print(kwargs)
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# MMCM
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if with_mmcm:
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platform.add_extension([
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("clkgen", 0,
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Subsignal("ref", Pins(1)),
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Subsignal("out0", Pins(1)),
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Subsignal("out1", Pins(1)),
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Subsignal("locked", Pins(1)),
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)
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])
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self.clock_domains.cd_out0 = ClockDomain(reset_less=True)
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self.clock_domains.cd_out1 = ClockDomain(reset_less=True)
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self.submodules.mmcm = mmcm = S7MMCM()
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mmcm.expose_drp()
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self.add_csr("mmcm")
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clkgen = platform.request("clkgen")
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mmcm.register_clkin(clkgen.ref, 100e6)
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mmcm.create_clkout(self.cd_out0, 148.5e6, with_reset=False)
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mmcm.create_clkout(self.cd_out1, 742.5e6, with_reset=False)
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self.comb += [
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clkgen.out0.eq(self.cd_out0.clk),
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clkgen.out1.eq(self.cd_out1.clk),
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clkgen.locked.eq(mmcm.locked),
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]
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# SPI Master
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if with_spi_master:
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platform.add_extension([
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("spi_master", 0,
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Subsignal("clk", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("mosi", Pins(1)),
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Subsignal("miso", Pins(1)),
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)
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])
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self.submodules.spi_master = SPIMaster(
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pads = platform.request("spi_master"),
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data_width = spi_master_data_width,
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sys_clk_freq = sys_clk_freq,
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spi_clk_freq = spi_master_clk_freq,
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)
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self.add_csr("spi_master")
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# PWM
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if with_pwm:
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platform.add_extension([("pwm", 0, Pins(1))])
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self.submodules.pwm = PWM(platform.request("pwm"))
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self.add_csr("pwm")
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# GPIO
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if with_gpio:
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platform.add_extension([("gpio", 0, Pins(gpio_width))])
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self.submodules.gpio = GPIOTristate(platform.request("gpio"))
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self.add_csr("gpio")
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# Wishbone Master
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if kwargs["bus"] in ["wishbone"]:
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wb_bus = wishbone.Interface()
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self.bus.add_master(master=wb_bus)
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platform.add_extension(wb_bus.get_ios("wb"))
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wb_pads = platform.request("wb")
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self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
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# AXI-Lite Master
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if kwargs["bus"] in ["axi", "axi_lite"]:
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axi_bus = axi.AXILiteInterface(data_width=32, address_width=32)
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wb_bus = wishbone.Interface()
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axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus)
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self.submodules += axi2wb
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self.bus.add_master(master=wb_bus)
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platform.add_extension(axi_bus.get_ios("axi"))
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axi_pads = platform.request("axi")
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self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
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# IRQs
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for name, loc in sorted(self.irq.locs.items()):
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module = getattr(self, name)
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platform.add_extension([("irq_"+name, 0, Pins(1))])
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irq_pin = platform.request("irq_"+name)
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self.comb += irq_pin.eq(module.ev.irq)
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# Build -------------------------------------------------------------------------------------------
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def soc_argdict(args):
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ret = {}
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for arg in [
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"bus",
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"with_pwm",
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"with_mmcm",
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"with_uart",
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"uart_fifo_depth",
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"with_ctrl",
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"with_timer",
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"with_gpio",
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"gpio_width",
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"with_spi_master",
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"spi_master_data_width",
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"spi_master_clk_freq",
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"csr_data_width",
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"csr_address_width",
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"csr_paging"]:
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ret[arg] = getattr(args, arg)
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return ret
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def main():
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parser = argparse.ArgumentParser(description="LiteX standalone core generator", formatter_class=argparse.ArgumentDefaultsHelpFormatter)
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builder_args(parser)
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# Bus
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parser.add_argument("--bus", default="wishbone", type=str, help="Bus Standard (wishbone, or axi-lite).")
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# Cores
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parser.add_argument("--with-pwm", action="store_true", help="Add PWM core.")
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parser.add_argument("--with-mmcm", action="store_true", help="Add MMCM (Xilinx 7-series) core.")
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parser.add_argument("--with-uart", action="store_true", help="Add UART core.")
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parser.add_argument("--uart-fifo-depth", default=16, type=int, help="UART FIFO depth.")
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parser.add_argument("--with-ctrl", action="store_true", help="Add bus controller core.")
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parser.add_argument("--with-timer", action="store_true", help="Add timer core.")
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parser.add_argument("--with-spi-master", action="store_true", help="Add SPI master core.")
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parser.add_argument("--spi-master-data-width", default=8, type=int, help="SPI master data width.")
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parser.add_argument("--spi-master-clk-freq", default=8e6, type=int, help="SPI master output clock frequency.")
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parser.add_argument("--with-gpio", action="store_true", help="Add GPIO core.")
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parser.add_argument("--gpio-width", default=32, type=int, help="GPIO signals width.")
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# CSR settings
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parser.add_argument("--csr-data-width", default=8, type=int, help="CSR bus data-width (8 or 32).")
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parser.add_argument("--csr-address-width", default=14, type=int, help="CSR bus address-width.")
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parser.add_argument("--csr-paging", default=0x800, type=int, help="CSR bus paging.")
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args = parser.parse_args()
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soc = LiteXCore(**soc_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,126 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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"""
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LiteX standalone SoC generator.
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This generator reduces the scope of LiteX to CPU/Peripherals selection/integration and to the creation
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of SoC with MMAP/Streaming DMA interfaces that can be reintegrated in external designs (or LiteX SoC).
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Think of it as a mini Nios SOPC Builder/ Zynq or Microblaze Subsystem generator that offers you the
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possibility to reuse any of CPU supported by LiteX :)
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"""
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import argparse
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from migen import *
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from litex.build.generic_platform import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import axi
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# IOs/Interfaces -----------------------------------------------------------------------------------
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def get_common_ios():
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return [
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# Clk/Rst.
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("clk", 0, Pins(1)),
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("rst", 0, Pins(1)),
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]
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def get_uart_ios():
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return [
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# Serial
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("uart", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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)
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GenericPlatform):
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def build(self, fragment, build_dir, build_name, **kwargs):
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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conv_output = self.get_verilog(fragment, name=build_name)
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conv_output.write(f"{build_name}.v")
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# LiteX SoC Generator ------------------------------------------------------------------------------
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class LiteXSoCGenerator(SoCMini):
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def __init__(self, name="litex_soc", sys_clk_freq=int(50e6), **kwargs):
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# Platform ---------------------------------------------------------------------------------
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platform = Platform(device="", io=get_common_ios())
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platform.name = name
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platform.add_extension(get_uart_ios())
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(
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clk = platform.request("clk"),
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rst = platform.request("rst"),
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)
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# SoC --------------------------------------------------------------------------------------
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "uart"
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# MMAP Slave Interface ---------------------------------------------------------------------
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s_bus = {
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"wishbone" : wishbone.Interface(),
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"axi-lite" : axi.AXILiteInterface(),
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}[kwargs["bus_standard"]]
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self.bus.add_master(name="mmap_s", master=s_bus)
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platform.add_extension(s_bus.get_ios("mmap_s"))
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wb_pads = platform.request("mmap_s")
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self.comb += s_bus.connect_to_pads(wb_pads, mode="slave")
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# MMAP Master Interface --------------------------------------------------------------------
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# FIXME: Allow Region configuration.
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m_bus = {
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"wishbone" : wishbone.Interface(),
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"axi-lite" : axi.AXILiteInterface(),
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}[kwargs["bus_standard"]]
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wb_region = SoCRegion(origin=0x2000_0000, size=0x1000_0000, cached=True) # FIXME.
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self.bus.add_slave(name="mmap_m", slave=m_bus, region=wb_region)
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platform.add_extension(m_bus.get_ios("mmap_m"))
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wb_pads = platform.request("mmap_m")
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self.comb += m_bus.connect_to_pads(wb_pads, mode="master")
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# Build --------------------------------------------------------------------------------------------
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def main():
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# Arguments.
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX standalone SoC generator")
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target_group = parser.add_argument_group(title="Generator options")
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target_group.add_argument("--name", default="litex_soc", help="SoC Name.")
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target_group.add_argument("--build", action="store_true", help="Build SoC.")
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target_group.add_argument("--sys-clk-freq", default=int(50e6), help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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# SoC.
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soc = LiteXSoCGenerator(
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name = args.name,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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# Build.
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builder = Builder(soc, **builder_argdict(args))
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builder.build(build_name=args.name, run=args.build)
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if __name__ == "__main__":
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main()
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