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Merge pull request #948 from developandplay/non-interactive

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Expose non-interactive mode
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enjoy-digital 2021-06-18 13:27:18 +02:00 committed by GitHub
commit e7d04a2d1b
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2 changed files with 6 additions and 3 deletions
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5
litex/build/sim/verilator.py
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@ -189,7 +189,8 @@ class SimVerilatorToolchain:
trace_fst = False,
trace_start = 0,
trace_end = -1,
regular_comb = False):
regular_comb = False,
interactive = True):
# Create build directory
os.makedirs(build_dir, exist_ok=True)
@ -238,7 +239,7 @@ class SimVerilatorToolchain:
run_as_root = True
if sim_config.has_module("xgmii_ethernet"):
run_as_root = True
_run_sim(build_name, as_root=run_as_root)
_run_sim(build_name, as_root=run_as_root, interactive=interactive)
os.chdir(cwd)

4
litex/tools/litex_sim.py
View file

@ -374,6 +374,7 @@ def sim_args(parser):
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
parser.add_argument("--sim-debug", action="store_true", help="Add simulation debugging modules")
parser.add_argument("--gtkwave-savefile", action="store_true", help="Generate GTKWave savefile")
parser.add_argument("--non-interactive", action="store_true", help="Run simulation without user input")
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
@ -452,7 +453,8 @@ def main():
trace = args.trace,
trace_fst = args.trace_fst,
trace_start = trace_start,
trace_end = trace_end
trace_end = trace_end,
interactive = not args.non_interactive
)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")