mirror of
https://github.com/enjoy-digital/litex.git
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move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
This commit is contained in:
Florent Kermarrec
parent
225a2d4704
commit
e82531cdf8
4 changed files with 0 additions and 585 deletions
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@ -1,38 +0,0 @@
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from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bus import lasmibus
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from migen.sim.generic import run_simulation
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def my_generator(n):
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bank = n % 4
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for x in range(4):
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t = TWrite(4*bank+x, 0x1000*bank + 0x100*x)
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yield t
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print("{0}: Wrote in {1} cycle(s)".format(n, t.latency))
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for x in range(4):
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t = TRead(4*bank+x)
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yield t
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print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency))
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assert(t.data == 0x1000*bank + 0x100*x)
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class MyModel(lasmibus.TargetModel):
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def read(self, bank, address):
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r = 0x1000*bank + 0x100*address
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#print("read from bank {0} address {1} -> {2:x}".format(bank, address, r))
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return r
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def write(self, bank, address, data, we):
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print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data))
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assert(data == 0x1000*bank + 0x100*address)
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class TB(Module):
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def __init__(self):
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self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4,
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read_latency=4, write_latency=1)
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self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 2)
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self.initiators = [lasmibus.Initiator(my_generator(n), self.xbar.get_master()) for n in range(4)]
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self.submodules += self.initiators
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if __name__ == "__main__":
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run_simulation(TB())
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@ -1,67 +0,0 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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def phase_cmd_description(a, ba):
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return [
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("address", a, DIR_M_TO_S),
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("bank", ba, DIR_M_TO_S),
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("cas_n", 1, DIR_M_TO_S),
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("cs_n", 1, DIR_M_TO_S),
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("ras_n", 1, DIR_M_TO_S),
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("we_n", 1, DIR_M_TO_S),
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("cke", 1, DIR_M_TO_S),
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("odt", 1, DIR_M_TO_S),
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("reset_n", 1, DIR_M_TO_S)
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]
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def phase_wrdata_description(d):
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return [
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("wrdata", d, DIR_M_TO_S),
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("wrdata_en", 1, DIR_M_TO_S),
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("wrdata_mask", d//8, DIR_M_TO_S)
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]
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def phase_rddata_description(d):
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return [
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("rddata_en", 1, DIR_M_TO_S),
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("rddata", d, DIR_S_TO_M),
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("rddata_valid", 1, DIR_S_TO_M)
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]
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def phase_description(a, ba, d):
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r = phase_cmd_description(a, ba)
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r += phase_wrdata_description(d)
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r += phase_rddata_description(d)
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return r
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class Interface(Record):
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def __init__(self, a, ba, d, nphases=1):
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layout = [("p"+str(i), phase_description(a, ba, d)) for i in range(nphases)]
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Record.__init__(self, layout)
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self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
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for p in self.phases:
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p.cas_n.reset = 1
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p.cs_n.reset = 1
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p.ras_n.reset = 1
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p.we_n.reset = 1
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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def get_standard_names(self, m2s=True, s2m=True):
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r = []
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add_suffix = len(self.phases) > 1
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for n, phase in enumerate(self.phases):
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for field, size, direction in phase.layout:
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if (m2s and direction == DIR_M_TO_S) or (s2m and direction == DIR_S_TO_M):
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if add_suffix:
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if direction == DIR_M_TO_S:
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suffix = "_p" + str(n)
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else:
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suffix = "_w" + str(n)
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else:
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suffix = ""
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r.append(("dfi_" + field + suffix, getattr(phase, field)))
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return r
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class Interconnect(Module):
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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@ -1,309 +0,0 @@
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from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import optree
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class Interface(Record):
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def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
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self.aw = aw
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self.dw = dw
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self.nbanks = nbanks
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self.req_queue_size = req_queue_size
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self.read_latency = read_latency
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self.write_latency = write_latency
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bank_layout = [
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("adr", aw, DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("req_ack", 1, DIR_S_TO_M),
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("dat_ack", 1, DIR_S_TO_M),
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("lock", 1, DIR_S_TO_M)
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]
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if nbanks > 1:
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layout = [("bank"+str(i), bank_layout) for i in range(nbanks)]
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else:
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layout = bank_layout
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layout += [
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("dat_w", dw, DIR_M_TO_S),
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("dat_we", dw//8, DIR_M_TO_S),
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("dat_r", dw, DIR_S_TO_M)
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]
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Record.__init__(self, layout)
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def _getattr_all(l, attr):
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it = iter(l)
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r = getattr(next(it), attr)
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for e in it:
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if getattr(e, attr) != r:
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raise ValueError
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return r
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class Crossbar(Module):
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def __init__(self, controllers, cba_shift):
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self._controllers = controllers
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self._cba_shift = cba_shift
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self._rca_bits = _getattr_all(controllers, "aw")
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self._dw = _getattr_all(controllers, "dw")
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self._nbanks = _getattr_all(controllers, "nbanks")
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self._req_queue_size = _getattr_all(controllers, "req_queue_size")
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self._read_latency = _getattr_all(controllers, "read_latency")
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self._write_latency = _getattr_all(controllers, "write_latency")
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self._bank_bits = log2_int(self._nbanks, False)
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self._controller_bits = log2_int(len(self._controllers), False)
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self._masters = []
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def get_master(self):
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if self.finalized:
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raise FinalizeError
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lasmi_master = Interface(self._rca_bits + self._bank_bits + self._controller_bits,
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self._dw, 1, self._req_queue_size, self._read_latency, self._write_latency)
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self._masters.append(lasmi_master)
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return lasmi_master
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def do_finalize(self):
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nmasters = len(self._masters)
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m_ca, m_ba, m_rca = self._split_master_addresses(self._controller_bits,
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self._bank_bits, self._rca_bits, self._cba_shift)
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for nc, controller in enumerate(self._controllers):
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if self._controller_bits:
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controller_selected = [ca == nc for ca in m_ca]
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else:
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controller_selected = [1]*nmasters
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master_req_acks = [0]*nmasters
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master_dat_acks = [0]*nmasters
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rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
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self.submodules += rrs
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for nb, rr in enumerate(rrs):
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bank = getattr(controller, "bank"+str(nb))
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# for each master, determine if another bank locks it
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master_locked = []
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for nm, master in enumerate(self._masters):
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locked = 0
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for other_nb, other_rr in enumerate(rrs):
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if other_nb != nb:
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other_bank = getattr(controller, "bank"+str(other_nb))
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locked = locked | (other_bank.lock & (other_rr.grant == nm))
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master_locked.append(locked)
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# arbitrate
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bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
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bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self._masters)]
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self.comb += [
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rr.request.eq(Cat(*bank_requested)),
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rr.ce.eq(~bank.stb & ~bank.lock)
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]
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# route requests
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self.comb += [
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bank.adr.eq(Array(m_rca)[rr.grant]),
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bank.we.eq(Array(self._masters)[rr.grant].we),
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bank.stb.eq(Array(bank_requested)[rr.grant])
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]
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master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
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for nm, master_req_ack in enumerate(master_req_acks)]
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master_dat_acks = [master_dat_ack | ((rr.grant == nm) & bank.dat_ack)
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for nm, master_dat_ack in enumerate(master_dat_acks)]
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self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
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self.comb += [master.dat_ack.eq(master_dat_ack) for master, master_dat_ack in zip(self._masters, master_dat_acks)]
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# route data writes
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controller_selected_wl = controller_selected
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for i in range(self._write_latency):
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n_controller_selected_wl = [Signal() for i in range(nmasters)]
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self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
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controller_selected_wl = n_controller_selected_wl
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dat_w_maskselect = []
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dat_we_maskselect = []
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for master, selected in zip(self._masters, controller_selected_wl):
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o_dat_w = Signal(self._dw)
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o_dat_we = Signal(self._dw//8)
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self.comb += If(selected,
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o_dat_w.eq(master.dat_w),
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o_dat_we.eq(master.dat_we)
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)
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dat_w_maskselect.append(o_dat_w)
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dat_we_maskselect.append(o_dat_we)
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self.comb += [
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controller.dat_w.eq(optree("|", dat_w_maskselect)),
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controller.dat_we.eq(optree("|", dat_we_maskselect))
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]
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# route data reads
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if self._controller_bits:
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for master in self._masters:
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controller_sel = Signal(self._controller_bits)
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for nc, controller in enumerate(self._controllers):
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for nb in range(nbanks):
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bank = getattr(controller, "bank"+str(nb))
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self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
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for i in range(self._read_latency):
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n_controller_sel = Signal(self._controller_bits)
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self.sync += n_controller_sel.eq(controller_sel)
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controller_sel = n_controller_sel
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self.comb += master.dat_r.eq(Array(self._controllers)[controller_sel].dat_r)
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else:
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self.comb += [master.dat_r.eq(self._controllers[0].dat_r) for master in self._masters]
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def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
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m_ca = [] # controller address
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m_ba = [] # bank address
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m_rca = [] # row and column address
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for master in self._masters:
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cba = Signal(self._controller_bits + self._bank_bits)
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rca = Signal(self._rca_bits)
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cba_upper = cba_shift + controller_bits + bank_bits
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self.comb += cba.eq(master.adr[cba_shift:cba_upper])
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if cba_shift < self._rca_bits:
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if cba_shift:
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self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
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else:
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self.comb += rca.eq(master.adr[cba_upper:])
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else:
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self.comb += rca.eq(master.adr[:cba_shift])
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if self._controller_bits:
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ca = Signal(self._controller_bits)
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ba = Signal(self._bank_bits)
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self.comb += Cat(ba, ca).eq(cba)
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else:
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ca = None
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ba = cba
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m_ca.append(ca)
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m_ba.append(ba)
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m_rca.append(rca)
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return m_ca, m_ba, m_rca
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class Initiator(Module):
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def __init__(self, generator, bus):
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self.generator = generator
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self.bus = bus
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self.transaction_start = 0
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self.transaction = None
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self.transaction_end = None
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def do_simulation(self, selfp):
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selfp.bus.dat_w = 0
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selfp.bus.dat_we = 0
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if self.transaction is not None:
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if selfp.bus.req_ack:
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selfp.bus.stb = 0
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if selfp.bus.dat_ack:
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if isinstance(self.transaction, TRead):
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self.transaction_end = selfp.simulator.cycle_counter + self.bus.read_latency
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else:
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self.transaction_end = selfp.simulator.cycle_counter + self.bus.write_latency - 1
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if self.transaction is None or selfp.simulator.cycle_counter == self.transaction_end:
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if self.transaction is not None:
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self.transaction.latency = selfp.simulator.cycle_counter - self.transaction_start - 1
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if isinstance(self.transaction, TRead):
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self.transaction.data = selfp.bus.dat_r
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else:
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selfp.bus.dat_w = self.transaction.data
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selfp.bus.dat_we = self.transaction.sel
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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raise StopSimulation
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if self.transaction is not None:
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self.transaction_start = selfp.simulator.cycle_counter
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selfp.bus.stb = 1
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selfp.bus.adr = self.transaction.address
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if isinstance(self.transaction, TRead):
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selfp.bus.we = 0
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else:
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selfp.bus.we = 1
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class TargetModel:
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def __init__(self):
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self.last_bank = 0
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def read(self, bank, address):
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return 0
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def write(self, bank, address, data, we):
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pass
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# Round-robin scheduling
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def select_bank(self, pending_banks):
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if not pending_banks:
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return -1
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self.last_bank += 1
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if self.last_bank > max(pending_banks):
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self.last_bank = 0
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while self.last_bank not in pending_banks:
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self.last_bank += 1
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return self.last_bank
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class _ReqFIFO(Module):
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def __init__(self, req_queue_size, bank):
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self.req_queue_size = req_queue_size
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self.bank = bank
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self.contents = []
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def do_simulation(self, selfp):
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if len(self.contents) < self.req_queue_size:
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if selfp.bank.stb:
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self.contents.append((selfp.bank.we, selfp.bank.adr))
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selfp.bank.req_ack = 1
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else:
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selfp.bank.req_ack = 0
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selfp.bank.lock = bool(self.contents)
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do_simulation.passive = True
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class Target(Module):
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def __init__(self, model, *ifargs, **ifkwargs):
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self.model = model
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self.bus = Interface(*ifargs, **ifkwargs)
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self.req_fifos = [_ReqFIFO(self.bus.req_queue_size, getattr(self.bus, "bank"+str(nb)))
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for nb in range(self.bus.nbanks)]
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self.submodules += self.req_fifos
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self.rd_pipeline = [None]*self.bus.read_latency
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self.wr_pipeline = [None]*(self.bus.write_latency + 1)
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def do_simulation(self, selfp):
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# determine banks with pending requests
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pending_banks = set(nb for nb, rf in enumerate(self.req_fifos) if rf.contents)
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# issue new transactions
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selected_bank_n = self.model.select_bank(pending_banks)
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selected_transaction = None
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for nb in range(self.bus.nbanks):
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bank = getattr(selfp.bus, "bank"+str(nb))
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if nb == selected_bank_n:
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bank.dat_ack = 1
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selected_transaction = self.req_fifos[nb].contents.pop(0)
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else:
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bank.dat_ack = 0
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rd_transaction = None
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wr_transaction = None
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if selected_bank_n >= 0:
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we, adr = selected_transaction
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if we:
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wr_transaction = selected_bank_n, adr
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else:
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rd_transaction = selected_bank_n, adr
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# data pipeline
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self.rd_pipeline.append(rd_transaction)
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self.wr_pipeline.append(wr_transaction)
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done_rd_transaction = self.rd_pipeline.pop(0)
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done_wr_transaction = self.wr_pipeline.pop(0)
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if done_rd_transaction is not None:
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selfp.bus.dat_r = self.model.read(done_rd_transaction[0], done_rd_transaction[1])
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if done_wr_transaction is not None:
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self.model.write(done_wr_transaction[0], done_wr_transaction[1],
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selfp.bus.dat_w, selfp.bus.dat_we)
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do_simulation.passive = True
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.bus import wishbone
|
||||
from migen.bank.description import *
|
||||
from migen.genlib.fsm import FSM, NextState
|
||||
from migen.genlib.misc import split, displacer, chooser
|
||||
from migen.genlib.record import Record, layout_len
|
||||
|
||||
# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
|
||||
class WB2LASMI(Module, AutoCSR):
|
||||
def __init__(self, cachesize, lasmim):
|
||||
self._cachesize = CSRStatus(8, reset=log2_int(cachesize))
|
||||
self.wishbone = wishbone.Interface()
|
||||
|
||||
###
|
||||
|
||||
data_width = flen(self.wishbone.dat_r)
|
||||
if lasmim.dw > data_width and (lasmim.dw % data_width) != 0:
|
||||
raise ValueError("LASMI data width must be a multiple of {dw}".format(dw=data_width))
|
||||
if lasmim.dw < data_width and (data_width % lasmim.dw) != 0:
|
||||
raise ValueError("WISHBONE data width must be a multiple of {dw}".format(dw=lasmim.dw))
|
||||
|
||||
# Split address:
|
||||
# TAG | LINE NUMBER | LINE OFFSET
|
||||
offsetbits = log2_int(max(lasmim.dw//data_width, 1))
|
||||
addressbits = lasmim.aw + offsetbits
|
||||
linebits = log2_int(cachesize) - offsetbits
|
||||
tagbits = addressbits - linebits
|
||||
wordbits = log2_int(max(data_width//lasmim.dw, 1))
|
||||
adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
|
||||
word = Signal(wordbits) if wordbits else None
|
||||
|
||||
# Data memory
|
||||
data_mem = Memory(lasmim.dw*2**wordbits, 2**linebits)
|
||||
data_port = data_mem.get_port(write_capable=True, we_granularity=8)
|
||||
self.specials += data_mem, data_port
|
||||
|
||||
write_from_lasmi = Signal()
|
||||
write_to_lasmi = Signal()
|
||||
if adr_offset is None:
|
||||
adr_offset_r = None
|
||||
else:
|
||||
adr_offset_r = Signal(offsetbits)
|
||||
self.sync += adr_offset_r.eq(adr_offset)
|
||||
|
||||
self.comb += [
|
||||
data_port.adr.eq(adr_line),
|
||||
If(write_from_lasmi,
|
||||
displacer(lasmim.dat_r, word, data_port.dat_w),
|
||||
displacer(Replicate(1, lasmim.dw//8), word, data_port.we)
|
||||
).Else(
|
||||
data_port.dat_w.eq(Replicate(self.wishbone.dat_w, max(lasmim.dw//data_width, 1))),
|
||||
If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
|
||||
displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
|
||||
)
|
||||
),
|
||||
If(write_to_lasmi,
|
||||
chooser(data_port.dat_r, word, lasmim.dat_w),
|
||||
lasmim.dat_we.eq(2**(lasmim.dw//8)-1)
|
||||
),
|
||||
chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
|
||||
]
|
||||
|
||||
|
||||
# Tag memory
|
||||
tag_layout = [("tag", tagbits), ("dirty", 1)]
|
||||
tag_mem = Memory(layout_len(tag_layout), 2**linebits)
|
||||
tag_port = tag_mem.get_port(write_capable=True)
|
||||
self.specials += tag_mem, tag_port
|
||||
tag_do = Record(tag_layout)
|
||||
tag_di = Record(tag_layout)
|
||||
self.comb += [
|
||||
tag_do.raw_bits().eq(tag_port.dat_r),
|
||||
tag_port.dat_w.eq(tag_di.raw_bits())
|
||||
]
|
||||
|
||||
self.comb += [
|
||||
tag_port.adr.eq(adr_line),
|
||||
tag_di.tag.eq(adr_tag)
|
||||
]
|
||||
if word is not None:
|
||||
self.comb += lasmim.adr.eq(Cat(word, adr_line, tag_do.tag))
|
||||
else:
|
||||
self.comb += lasmim.adr.eq(Cat(adr_line, tag_do.tag))
|
||||
|
||||
# Lasmim word computation, word_clr and word_inc will be simplified
|
||||
# at synthesis when wordbits=0
|
||||
word_clr = Signal()
|
||||
word_inc = Signal()
|
||||
if word is not None:
|
||||
self.sync += \
|
||||
If(word_clr,
|
||||
word.eq(0),
|
||||
).Elif(word_inc,
|
||||
word.eq(word+1)
|
||||
)
|
||||
|
||||
def word_is_last(word):
|
||||
if word is not None:
|
||||
return word == 2**wordbits-1
|
||||
else:
|
||||
return 1
|
||||
|
||||
# Control FSM
|
||||
assert(lasmim.write_latency >= 1 and lasmim.read_latency >= 1)
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.delayed_enter("EVICT_DATAD", "EVICT_DATA", lasmim.write_latency-1)
|
||||
fsm.delayed_enter("REFILL_DATAD", "REFILL_DATA", lasmim.read_latency-1)
|
||||
|
||||
fsm.act("IDLE",
|
||||
If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
|
||||
)
|
||||
fsm.act("TEST_HIT",
|
||||
word_clr.eq(1),
|
||||
If(tag_do.tag == adr_tag,
|
||||
self.wishbone.ack.eq(1),
|
||||
If(self.wishbone.we,
|
||||
tag_di.dirty.eq(1),
|
||||
tag_port.we.eq(1)
|
||||
),
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
If(tag_do.dirty,
|
||||
NextState("EVICT_REQUEST")
|
||||
).Else(
|
||||
NextState("REFILL_WRTAG")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("EVICT_REQUEST",
|
||||
lasmim.stb.eq(1),
|
||||
lasmim.we.eq(1),
|
||||
If(lasmim.req_ack, NextState("EVICT_WAIT_DATA_ACK"))
|
||||
)
|
||||
fsm.act("EVICT_WAIT_DATA_ACK",
|
||||
If(lasmim.dat_ack, NextState("EVICT_DATAD"))
|
||||
)
|
||||
fsm.act("EVICT_DATA",
|
||||
write_to_lasmi.eq(1),
|
||||
word_inc.eq(1),
|
||||
If(word_is_last(word),
|
||||
NextState("REFILL_WRTAG"),
|
||||
).Else(
|
||||
NextState("EVICT_REQUEST")
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("REFILL_WRTAG",
|
||||
# Write the tag first to set the LASMI address
|
||||
tag_port.we.eq(1),
|
||||
word_clr.eq(1),
|
||||
NextState("REFILL_REQUEST")
|
||||
)
|
||||
fsm.act("REFILL_REQUEST",
|
||||
lasmim.stb.eq(1),
|
||||
If(lasmim.req_ack, NextState("REFILL_WAIT_DATA_ACK"))
|
||||
)
|
||||
fsm.act("REFILL_WAIT_DATA_ACK",
|
||||
If(lasmim.dat_ack, NextState("REFILL_DATAD"))
|
||||
)
|
||||
fsm.act("REFILL_DATA",
|
||||
write_from_lasmi.eq(1),
|
||||
word_inc.eq(1),
|
||||
If(word_is_last(word),
|
||||
NextState("TEST_HIT"),
|
||||
).Else(
|
||||
NextState("REFILL_REQUEST")
|
||||
)
|
||||
)
|
||||
Loading…
Reference in a new issue