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fix uart startbit: 1 cycle later

This commit is contained in:
David Jablonski 2020-05-24 16:12:07 +02:00
parent b4267a7901
commit e853ad4b61
1 changed files with 6 additions and 3 deletions
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9
litex/soc/cores/uart.py
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@ -99,8 +99,7 @@ class RS232PHYTX(Module):
If(self.sink.valid & ~tx_busy & ~self.sink.ready,
tx_reg.eq(self.sink.data),
tx_bitcount.eq(0),
tx_busy.eq(1),
pads.tx.eq(0)
tx_busy.eq(1)
).Elif(uart_clk_txen & tx_busy,
tx_bitcount.eq(tx_bitcount + 1),
If(tx_bitcount == 8,
@ -113,6 +112,10 @@ class RS232PHYTX(Module):
pads.tx.eq(tx_reg[0]),
tx_reg.eq(Cat(tx_reg[1:], 0))
)
).Elif(tx_busy,
If(tx_bitcount == 0,
pads.tx.eq(0)
)
)
]
self.sync += [
@ -235,7 +238,7 @@ class UART(Module, AutoCSR, UARTInterface):
self._rxempty.status.eq(~rx_fifo.source.valid),
self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)),
# Generate RX IRQ when tx_fifo becomes non-empty
# Generate RX IRQ when rx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.valid)
]