Merge pull request #156 from gsomlo/gls-axi-width

soc/interconnect/axi: address length cleanup
This commit is contained in:
enjoy-digital 2019-03-28 18:27:36 +01:00 committed by GitHub
commit e8559990b6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 4 deletions

View File

@ -60,12 +60,12 @@ class AXIInterface(Record):
class AXI2Wishbone(Module): class AXI2Wishbone(Module):
def __init__(self, axi, wishbone, base_address): def __init__(self, axi, wishbone, base_address):
assert axi.data_width == 32 assert axi.data_width == len(wishbone.dat_r)
assert axi.address_width == 32 assert axi.address_width == len(wishbone.adr) + 2
_data = Signal(axi.data_width) _data = Signal(axi.data_width)
_read_addr = Signal(32) _read_addr = Signal(axi.address_width)
_write_addr = Signal(32) _write_addr = Signal(axi.address_width)
self.comb += _read_addr.eq(axi.ar.addr - base_address) self.comb += _read_addr.eq(axi.ar.addr - base_address)
self.comb += _write_addr.eq(axi.aw.addr - base_address) self.comb += _write_addr.eq(axi.aw.addr - base_address)