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litex
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do more test with last changes fix small issues

This commit is contained in:
Florent Kermarrec 2015-05-02 14:26:19 +02:00
parent 63b8797978
commit e8c01ff4aa
3 changed files with 3 additions and 3 deletions
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2
misoclib/com/liteusb/frontend/wishbone.py
View File

@ -1,7 +1,7 @@
from migen.fhdl.std import *
from misoclib.com.liteusb.common import *
from misoclib.tools.litescope.bridge.wishbone import LiteScopeWishboneBridge
from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
def __init__(self, port, clk_freq):

2
misoclib/com/liteusb/software/wishbone.py
View File

@ -5,7 +5,7 @@ class LiteUSBWishboneDriverFTDI:
"write": 0x01,
"read": 0x02
}
def __init__(self, interface, mode, tag, addrmap=None, debug=False):
def __init__(self, interface, mode, tag, addrmap=None, busword=8, debug=False):
self.interface = interface
self.mode = mode
self.tag = tag

2
software/common.mak
View File

@ -19,7 +19,7 @@ LD_quiet = @echo " LD " $@ && $(TARGET_PREFIX)ld
OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(TARGET_PREFIX)objcopy
RANLIB_quiet = @echo " RANLIB " $@ && $(TARGET_PREFIX)ranlib
MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.peripherals.identifier.git import get_id; print(hex(get_id()), end='')")
MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.git import get_id; print(hex(get_id()), end='')")
ifeq ($(V),1)
CC = $(CC_normal)