do more test with last changes fix small issues
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parent
63b8797978
commit
e8c01ff4aa
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@ -1,7 +1,7 @@
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from misoclib.com.liteusb.common import *
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from misoclib.com.liteusb.common import *
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from misoclib.tools.litescope.bridge.wishbone import LiteScopeWishboneBridge
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from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
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class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
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class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
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def __init__(self, port, clk_freq):
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def __init__(self, port, clk_freq):
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@ -5,7 +5,7 @@ class LiteUSBWishboneDriverFTDI:
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"write": 0x01,
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"write": 0x01,
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"read": 0x02
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"read": 0x02
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}
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}
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def __init__(self, interface, mode, tag, addrmap=None, debug=False):
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def __init__(self, interface, mode, tag, addrmap=None, busword=8, debug=False):
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self.interface = interface
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self.interface = interface
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self.mode = mode
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self.mode = mode
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self.tag = tag
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self.tag = tag
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@ -19,7 +19,7 @@ LD_quiet = @echo " LD " $@ && $(TARGET_PREFIX)ld
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OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(TARGET_PREFIX)objcopy
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OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(TARGET_PREFIX)objcopy
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RANLIB_quiet = @echo " RANLIB " $@ && $(TARGET_PREFIX)ranlib
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RANLIB_quiet = @echo " RANLIB " $@ && $(TARGET_PREFIX)ranlib
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MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.peripherals.identifier.git import get_id; print(hex(get_id()), end='')")
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MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.git import get_id; print(hex(get_id()), end='')")
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ifeq ($(V),1)
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ifeq ($(V),1)
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CC = $(CC_normal)
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CC = $(CC_normal)
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