soc/add_sdram: avoid L2 cache when l2_cache_size == 0.

litex/soc/integration/soc.py

@@ -944,16 +944,17 @@ class LiteXSoC(SoC):
                     base_address = origin)
                 self.submodules += wishbone.Converter(mem_wb, litedram_wb)
         elif self.with_wishbone:
+            # Wishbone Slave SDRAM interface -------------------------------------------------------
+            wb_sdram = wishbone.Interface()
+            self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size))
+
+            if l2_cache_size != 0:
                 # Insert L2 cache inbetween Wishbone bus and LiteDRAM
                 l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
                 l2_cache_size = 2**int(log2(l2_cache_size))                  # Round to nearest power of 2
                 self.add_config("L2_SIZE", l2_cache_size)
 
-            # SoC <--> L2 Cache Wishbone interface -------------------------------------------------
+                # L2 Cache -------------------------------------------------------------------------
-            wb_sdram = wishbone.Interface()
-            self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size))
-
-            # L2 Cache -----------------------------------------------------------------------------
                 l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
                 l2_cache = wishbone.Cache(
                     cachesize = l2_cache_size//4,
@@ -967,6 +968,11 @@ class LiteXSoC(SoC):
                     self.submodules.l2_cache = FullMemoryWE()(l2_cache)
                 else:
                     self.submodules.l2_cache = l2_cache
-
+                # L2 Cache <--> LiteDRAM bridge ----------------------------------------------------
-            # L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
                 self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
+            else:
+                self.add_config("L2_SIZE", l2_cache_size)
+                litedram_wb = wishbone.Interface(port.data_width)
+                self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
+                # Wishbone Slave <--> LiteDRAM bridge ----------------------------------------------
+                self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)