soc/add_sdram: avoid L2 cache when l2_cache_size == 0.

This commit is contained in:
Florent Kermarrec 2020-02-10 19:02:44 +01:00
parent dcbdb73231
commit e8e4537e14
1 changed files with 28 additions and 22 deletions

View File

@ -944,29 +944,35 @@ class LiteXSoC(SoC):
base_address = origin) base_address = origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb) self.submodules += wishbone.Converter(mem_wb, litedram_wb)
elif self.with_wishbone: elif self.with_wishbone:
# Insert L2 cache inbetween Wishbone bus and LiteDRAM # Wishbone Slave SDRAM interface -------------------------------------------------------
l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
self.add_config("L2_SIZE", l2_cache_size)
# SoC <--> L2 Cache Wishbone interface -------------------------------------------------
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()
self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size)) self.bus.add_slave("main_ram", wb_sdram, SoCRegion(origin=origin, size=sdram_size))
# L2 Cache ----------------------------------------------------------------------------- if l2_cache_size != 0:
l2_cache_data_width = max(port.data_width, l2_cache_min_data_width) # Insert L2 cache inbetween Wishbone bus and LiteDRAM
l2_cache = wishbone.Cache( l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
cachesize = l2_cache_size//4, l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
master = wb_sdram, self.add_config("L2_SIZE", l2_cache_size)
slave = wishbone.Interface(l2_cache_data_width),
reverse = l2_cache_reverse)
# XXX Vivado workaround, Vivado is not able to map correctly our L2 cache.
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
# L2 Cache <--> LiteDRAM bridge -------------------------------------------------------- # L2 Cache -------------------------------------------------------------------------
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
l2_cache = wishbone.Cache(
cachesize = l2_cache_size//4,
master = wb_sdram,
slave = wishbone.Interface(l2_cache_data_width),
reverse = l2_cache_reverse)
# XXX Vivado workaround, Vivado is not able to map correctly our L2 cache.
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
# L2 Cache <--> LiteDRAM bridge ----------------------------------------------------
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
else:
self.add_config("L2_SIZE", l2_cache_size)
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
# Wishbone Slave <--> LiteDRAM bridge ----------------------------------------------
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)