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Merge pull request #309 from antmicro/mmcm-fix 

soc/cores/clock: add lock reg and assign reset
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enjoy-digital 2019-11-20 19:20:15 +01:00 committed by GitHub
parent 04017519c8 fd14b76594
commit e8e70b164a
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1 changed files with 2 additions and 1 deletions
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litex/soc/cores/clock.py
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@ -92,6 +92,7 @@ class XilinxClocking(Module, AutoCSR):
def expose_drp(self):
self.drp_reset = CSR()
self.drp_locked = CSR()
self.drp_read = CSR()
self.drp_write = CSR()
self.drp_drdy = CSRStatus()
@ -261,7 +262,7 @@ class S7MMCM(XilinxClocking):
config = self.compute_config()
mmcm_fb = Signal()
self.params.update(
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,