build/sim/verilator: cleanup SimVerilatorToolchain, return to initial path after build/run.
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222e3f4003
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@ -173,43 +173,58 @@ def _run_sim(build_name, as_root=False):
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class SimVerilatorToolchain:
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def build(self, platform, fragment, build_dir="build", build_name="sim",
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serial="console", build=True, run=True, threads=1,
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verbose=True, sim_config=None, coverage=False, opt_level="O0",
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trace=False, trace_fst=False, trace_start=0, trace_end=-1,
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "sim",
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serial = "console",
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build = True,
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run = True,
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threads = 1,
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verbose = True,
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sim_config = None,
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coverage = False,
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opt_level = "O0",
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trace = False,
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trace_fst = False,
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trace_start = 0,
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trace_end = -1,
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regular_comb = False):
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# create build directory
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# Create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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if build:
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# finalize design
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# generate top module
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top_output = platform.get_verilog(fragment,
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name=build_name, dummy_signal=False, regular_comb=regular_comb, blocking_assign=True)
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named_sc, named_pc = platform.resolve_signals(top_output.ns)
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top_file = build_name + ".v"
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top_output.write(top_file)
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platform.add_source(top_file)
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# Generate verilog
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v_output = platform.get_verilog(fragment,
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name = build_name,
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dummy_signal = False,
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regular_comb = regular_comb,
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blocking_assign = True)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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# generate cpp header/main/variables
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# Generate cpp header/main/variables
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_generate_sim_h(platform)
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_generate_sim_cpp(platform, trace, trace_start, trace_end)
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_generate_sim_variables(platform.verilog_include_paths)
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# generate sim config
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# Generate sim config
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if sim_config:
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_generate_sim_config(sim_config)
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# build
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# Build
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_build_sim(build_name, platform.sources, threads, coverage, opt_level, trace_fst)
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# run
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# Run
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if run:
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_compile_sim(build_name, verbose)
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run_as_root = False
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@ -219,7 +234,7 @@ class SimVerilatorToolchain:
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run_as_root = True
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_run_sim(build_name, as_root=run_as_root)
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os.chdir("../../")
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os.chdir(cwd)
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if build:
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return top_output.ns
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return v_output.ns
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