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mibuild/xilinx_ise: move overwrite option to default options
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1 changed files with 6 additions and 6 deletions
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@ -148,9 +148,9 @@ xst -ifn {build_name}.xst"""
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build_script_contents += """
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ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd
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map {map_opt} -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
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par {par_opt} -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
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bitgen {bitgen_opt} -w {build_name}.ncd {build_name}.bit
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map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
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par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
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bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
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"""
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build_script_contents = build_script_contents.format(build_name=build_name,
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ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext,
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@ -188,10 +188,10 @@ class XilinxISEPlatform(GenericPlatform):
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-opt_mode SPEED
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-reduce_control_sets auto
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-register_balancing yes"""
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map_opt = "-ol high"
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par_opt = "-ol high"
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map_opt = "-ol high -w"
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par_opt = "-ol high -w"
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ngdbuild_opt = ""
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes"
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w"
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ise_commands = ""
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = {
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