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soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower

This commit is contained in:
Florent Kermarrec 2019-09-19 05:16:01 +02:00
parent 99ed0877ac
commit e97c1e36fb
1 changed files with 42 additions and 31 deletions
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31
litex/soc/integration/soc_sdram.py
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@ -18,6 +18,9 @@ from litedram import dfii, core
__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
# Controller Injector ------------------------------------------------------------------------------
# FIXME: move to LiteDRAM
class ControllerInjector(Module, AutoCSR): class ControllerInjector(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs): def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
@ -36,6 +39,7 @@ class ControllerInjector(Module, AutoCSR):
self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface) self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface)
# SoCSDRAM -----------------------------------------------------------------------------------------
class SoCSDRAM(SoCCore): class SoCSDRAM(SoCCore):
csr_map = { csr_map = {
@ -64,24 +68,29 @@ class SoCSDRAM(SoCCore):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
# LiteDRAM core -------------------------------------------------------------------------------
self.submodules.sdram = ControllerInjector( self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, self.clk_freq, **kwargs) phy, geom_settings, timing_settings, self.clk_freq, **kwargs)
# LiteDRAM port -------------------------------------------------------------------------------
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
# Parameters ------ ------------------------------------------------------------------------
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8 geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
self.config["L2_SIZE"] = self.l2_size
# add a Wishbone interface to the DRAM l2_size = 2**int(log2(self.l2_size)) # Round to nearest power of 2
l2_size = max(l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower
# SoC <--> L2 Cache Wishbone interface -----------------------------------------------------
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram) self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
if self.l2_size: # L2 Cache ---------------------------------------------------------------------------------
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
l2_size = 2**int(log2(self.l2_size)) # Round to nearest power of 2
l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
# XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
@ -91,6 +100,9 @@ class SoCSDRAM(SoCCore):
self.submodules.l2_cache = FullMemoryWE()(l2_cache) self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else: else:
self.submodules.l2_cache = l2_cache self.submodules.l2_cache = l2_cache
self.config["L2_SIZE"] = l2_size
# L2 Cache <--> LiteDRAM bridge ------------------------------------------------------------
if use_axi: if use_axi:
axi_port = LiteDRAMAXIPort( axi_port = LiteDRAMAXIPort(
port.data_width, port.data_width,
@ -104,11 +116,10 @@ class SoCSDRAM(SoCCore):
def do_finalize(self): def do_finalize(self):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
if not self._sdram_phy: if not self._sdram_phy:
raise FinalizeError("Need to call SDRAMSoC.register_sdram()") raise FinalizeError("Need to call SoCSDRAM.register_sdram()")
# arbitrate wishbone interfaces to the DRAM # Arbitrate wishbone interfaces to the DRAM
self.submodules.wb_sdram_con = wishbone.Arbiter( self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram)
self._wb_sdram_ifs, self._wb_sdram)
SoCCore.do_finalize(self) SoCCore.do_finalize(self)