Merge pull request #1091 from enjoy-digital/memory-dev
fhdl/memory: Improve generation code and avoid specific generation for Efinix FPGAs.
This commit is contained in:
enjoy-digital
GitHub
commit
e9dd07006e
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@ -18,12 +18,12 @@ import datetime
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from xml.dom import expatbuilder
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import xml.etree.ElementTree as et
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from litex.build.generic_platform import *
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from migen.fhdl.structure import _Fragment
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from migen.fhdl.tools import *
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from migen.fhdl.namer import build_namespace
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from migen.fhdl.simplify import FullMemoryWE
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from litex.build.generic_platform import *
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from litex.build.generic_platform import Pins, IOStandard, Misc
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from litex.build import tools
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@ -268,6 +268,9 @@ class EfinityToolchain:
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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# Apply FullMemoryWE on design (Efiniy does not infer memories correctly otherwise).
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FullMemoryWE()(fragment)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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@ -1,3 +1,10 @@
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#
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# This file is part of LiteX (Adapted from Migen for LiteX usage).
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#
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# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.fhdl.bitcontainer import bits_for
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@ -6,91 +13,143 @@ from migen.fhdl.verilog import _printexpr as verilog_printexpr
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from migen.fhdl.specials import *
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def memory_emit_verilog(memory, ns, add_data_file):
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r = ""
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# Helpers.
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# --------
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def gn(e):
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if isinstance(e, Memory):
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return ns.get_name(e)
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else:
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return verilog_printexpr(ns, e)[0]
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adrbits = bits_for(memory.depth-1)
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(memory) \
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+ "[0:" + str(memory.depth-1) + "];\n"
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# Parameters.
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# -----------
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r = ""
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adr_regs = {}
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data_regs = {}
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# https://github.com/enjoy-digital/litex/issues/1003
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# FIXME: Verify behaviour with the different FPGA toolchains.
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# Ports Transformations.
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# ----------------------
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# Set Port Mode to Read-First when several Ports with different Clocks.
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# FIXME: Verify behaviour with the different FPGA toolchains, try to avoid it.
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clocks = [port.clock for port in memory.ports]
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if clocks.count(clocks[0]) != len(clocks):
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for port in memory.ports:
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port.mode = READ_FIRST
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# Set Port Granularity when 0.
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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adr_regs[id(port)] = adr_reg
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else:
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data_reg = Signal(name_override="memdat")
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(data_reg) + ";\n"
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data_regs[id(port)] = data_reg
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if port.we_granularity == 0:
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port.we_granularity = memory.width
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for port in memory.ports:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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if port.we is not None:
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if port.we_granularity:
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n = memory.width//port.we_granularity
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for i in range(n):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n"
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# Memory Description.
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# -------------------
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r += "//" + "-"*80 + "\n"
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r += f"// Memory {gn(memory)}: {memory.depth}-words x {memory.width}-bit\n"
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r += "//" + "-"*80 + "\n"
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for n, port in enumerate(memory.ports):
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r += f"// Port {n} | "
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if port.async_read:
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r += "Read: Async | "
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else:
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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if not port.async_read:
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r += "Read: Sync | "
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if port.we is None:
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r += "Write: ---- | "
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else:
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r += "Write: Sync | "
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r += "Mode: "
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if port.mode == WRITE_FIRST:
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
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if port.mode == READ_FIRST:
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rd = "\t" + bassign
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r += "Write-First | "
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elif port.mode == READ_FIRST:
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r += "Read-First | "
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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+ "\t\t" + bassign
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r += "No-Change | "
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r += f"Write-Granularity: {port.we_granularity} "
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r += "\n"
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# Memory Logic Declaration/Initialization.
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# ----------------------------------------
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r += f"reg [{memory.width-1}:0] {gn(memory)}[0:{memory.depth-1}];\n"
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if memory.init is not None:
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content = ""
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formatter = f"{{:0{int(memory.width/4)}x}}\n"
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for d in memory.init:
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content += formatter.format(d)
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memory_filename = add_data_file(f"{gn(memory)}.init", content)
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r += "initial begin\n"
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r += f"\t$readmemh(\"{memory_filename}\", {gn(memory)});\n"
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r += "end\n"
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# Port Intermediate Signals.
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# --------------------------
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for n, port in enumerate(memory.ports):
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# No Intermediate Signal for Async Read.
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if port.async_read:
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continue
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# Create Address Register in Write-First mode.
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if port.mode in [WRITE_FIRST]:
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adr_regs[n] = Signal(name_override=f"{gn(memory)}_adr{n}")
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r += f"reg [{bits_for(memory.depth-1)-1}:0] {gn(adr_regs[n])};\n"
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# Create Data Register in Read-First/No Change mode.
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if port.mode in [READ_FIRST, NO_CHANGE]:
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data_regs[n] = Signal(name_override=f"{gn(memory)}_dat{n}")
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r += f"reg [{memory.width-1}:0] {gn(data_regs[n])};\n"
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# Ports Write/Read Logic.
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# -----------------------
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for n, port in enumerate(memory.ports):
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r += f"always @(posedge {gn(port.clock)}) begin\n"
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# Write Logic.
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if port.we is not None:
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# Split Write Logic.
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for i in range(memory.width//port.we_granularity):
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wbit = f"[{i}]" if memory.width != port.we_granularity else ""
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r += f"\tif ({gn(port.we)}{wbit})\n"
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lbit = i*port.we_granularity
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hbit = (i+1)*port.we_granularity-1
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r += f"\t\t{gn(memory)}[{gn(port.adr)}][{hbit}:{lbit}] <= {gn(port.dat_w)}[{hbit}:{lbit}];\n"
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# Read Logic.
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if not port.async_read:
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# In Write-First mode, Read from Address Register.
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if port.mode in [WRITE_FIRST]:
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rd = f"\t{gn(adr_regs[n])} <= {gn(port.adr)};\n"
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# In Read-First/No Change mode:
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if port.mode in [READ_FIRST, NO_CHANGE]:
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rd = ""
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# Only Read in No-Change mode when no Write.
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if port.mode == NO_CHANGE:
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rd += f"\tif (!{gn(port.we)})\n\t"
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# Read-First/No-Change Read logic.
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rd += f"\t{gn(data_regs[n])} <= {gn(memory)}[{gn(port.adr)}];\n"
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# Add Read-Enable Logic.
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if port.re is None:
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r += rd
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else:
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r += "\tif (" + gn(port.re) + ")\n"
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r += f"\tif ({gn(port.re)})\n"
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r += "\t" + rd.replace("\n\t", "\n\t\t")
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r += "end\n\n"
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r += "end\n"
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for port in memory.ports:
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# Ports Read Mapping.
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# -------------------
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for n, port in enumerate(memory.ports):
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# Direct (Asynchronous) Read on Async-Read mode.
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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r += "\n"
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r += f"assign {gn(port.dat_r)} = {gn(memory)}[{gn(port.adr)}];\n"
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continue
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if memory.init is not None:
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content = ""
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formatter = "{:0" + str(int(memory.width / 4)) + "X}\n"
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for d in memory.init:
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content += formatter.format(d)
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memory_filename = add_data_file(gn(memory) + ".init", content)
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# Write-First mode: Do Read through Address Register.
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if port.mode in [WRITE_FIRST]:
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r += f"assign {gn(port.dat_r)} = {gn(memory)}[{gn(adr_regs[n])}];\n"
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r += "initial begin\n"
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r += "\t$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
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r += "end\n\n"
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# Read-First/No-Change mode: Data already Read on Data Register.
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if port.mode in [READ_FIRST, NO_CHANGE]:
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r += f"assign {gn(port.dat_r)} = {gn(data_regs[n])};\n"
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r += "//" + "-"*80 + "\n\n"
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return r
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@ -1,132 +0,0 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.fhdl.bitcontainer import bits_for
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from migen.fhdl.tools import *
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from migen.fhdl.verilog import _printexpr as verilog_printexpr
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from migen.fhdl.specials import *
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def memory_emit_verilog(memory, ns, add_data_file):
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r = ""
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def gn(e):
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if isinstance(e, Memory):
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return ns.get_name(e)
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else:
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return verilog_printexpr(ns, e)[0]
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adrbits = bits_for(memory.depth-1)
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for i in range(memory.width // 8):
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r += "reg [" + str((memory.width//4)-1) + ":0] " \
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+ gn(memory) + '_efx_' + str(i) \
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+ "[0:" + str(memory.depth-1) + "];\n"
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adr_regs = {}
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data_regs = {}
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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adr_regs[id(port)] = adr_reg
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else:
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data_reg = Signal(name_override="memdat")
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(data_reg) + ";\n"
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data_regs[id(port)] = data_reg
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for port in memory.ports:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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if port.we is not None:
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if port.we_granularity:
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n = memory.width//port.we_granularity
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for i in range(n):
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if (i > 0):
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
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r += "\t\t" + gn(memory) + '_efx_' + str(i) + "[" + gn(port.adr) + "]" + " <= " + gn(port.dat_w) + sl + ";\n"
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r += "end\n"
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else:
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = ""
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for i in range(memory.width // 8):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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bassign += gn(data_regs[id(port)]) + sl + " <= " + gn(memory) + "_efx_" + str(i) + "[" + gn(port.adr) + "];\n"
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if port.mode == READ_FIRST:
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rd = "\t" + bassign
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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+ "\t\t" + bassign
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if port.re is None:
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r += rd
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else:
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r += "\tif (" + gn(port.re) + ")\n"
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r += "\t" + rd.replace("\n\t", "\n\t\t")
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r += "end\n\n"
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for port in memory.ports:
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST:
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for i in range(memory.width // 8):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "assign " + gn(port.dat_r) + sl + " = " + gn(memory) + "_efx_" + str(i) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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r += "\n"
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if memory.init is not None:
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content_7_0 = ""
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content_15_8 = ""
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content_23_16 = ""
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content_31_24 = ""
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formatter = "{:0" + str(int(memory.width / 4)) + "X}\n"
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init_7_0 = []
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init_15_8 = []
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init_23_16 = []
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init_31_24 = []
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for w in memory.init:
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init_7_0.append(w & 0xff)
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init_15_8.append((w >> 8) & 0xff)
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init_23_16.append((w >> 16) & 0xff)
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init_31_24.append((w >> 24) & 0xff)
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for d in init_7_0:
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content_7_0 += formatter.format(d)
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for d in init_15_8:
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content_15_8 += formatter.format(d)
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for d in init_23_16:
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content_23_16 += formatter.format(d)
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for d in init_31_24:
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content_31_24 += formatter.format(d)
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memory_filename1 = add_data_file(gn(memory) + "_efx_1.init", content_7_0)
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memory_filename2 = add_data_file(gn(memory) + "_efx_2.init", content_15_8)
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memory_filename3 = add_data_file(gn(memory) + "_efx_3.init", content_23_16)
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memory_filename4 = add_data_file(gn(memory) + "_efx_4.init", content_31_24)
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r += "initial begin\n"
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r += "\t$readmemh(\"" + memory_filename1 + "\", " + gn(memory)+ "_efx_0" + ");\n"
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r += "\t$readmemh(\"" + memory_filename2 + "\", " + gn(memory)+ "_efx_1" + ");\n"
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r += "\t$readmemh(\"" + memory_filename3 + "\", " + gn(memory)+ "_efx_2" + ");\n"
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r += "\t$readmemh(\"" + memory_filename4 + "\", " + gn(memory)+ "_efx_3" + ");\n"
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r += "end\n\n"
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return r
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@ -439,13 +439,8 @@ def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
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attr = _print_attribute(special.attr, attr_translate)
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if attr:
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r += attr + " "
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# Replace Migen Memory's emit_verilog with our implementation.
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# Replace Migen Memory's emit_verilog with LiteX's implementation.
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if isinstance(special, Memory):
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from litex.build.efinix.platform import EfinixPlatform
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if isinstance(special.platform, EfinixPlatform) and (special.width == 32): # FIXME: Improve.
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from litex.gen.fhdl.memory_efinix import memory_emit_verilog
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pr = memory_emit_verilog(special, ns, add_data_file)
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else:
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from litex.gen.fhdl.memory import memory_emit_verilog
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pr = memory_emit_verilog(special, ns, add_data_file)
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else:
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|||
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