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soc/cores/gpio: uniformize with others cores

This commit is contained in:
Florent Kermarrec 2019-09-29 16:10:44 +02:00
parent 78cecbe36b
commit e9ed4761b5
1 changed files with 3 additions and 0 deletions
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3
litex/soc/cores/gpio.py
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@ -6,18 +6,21 @@ from migen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
# GPIO Input ----------------------------------------------------------------------------------------
class GPIOIn(Module, AutoCSR): class GPIOIn(Module, AutoCSR):
def __init__(self, signal): def __init__(self, signal):
self._in = CSRStatus(len(signal)) self._in = CSRStatus(len(signal))
self.specials += MultiReg(signal, self._in.status) self.specials += MultiReg(signal, self._in.status)
# GPIO Output --------------------------------------------------------------------------------------
class GPIOOut(Module, AutoCSR): class GPIOOut(Module, AutoCSR):
def __init__(self, signal): def __init__(self, signal):
self._out = CSRStorage(len(signal)) self._out = CSRStorage(len(signal))
self.comb += signal.eq(self._out.storage) self.comb += signal.eq(self._out.storage)
# GPIO Input/Output --------------------------------------------------------------------------------
class GPIOInOut(Module): class GPIOInOut(Module):
def __init__(self, in_signal, out_signal): def __init__(self, in_signal, out_signal):