soc/cores/cpu/vexriscv: add add_debug method for debug variants
This commit is contained in:
Florent Kermarrec
parent
35155e5172
commit
e9f1049200
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@ -19,16 +19,11 @@ class VexRiscv(Module, AutoCSR):
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variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
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assert variant in variants, "Unsupported variant %s" % variant
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self.reset = Signal()
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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i_err = Signal()
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d_err = Signal()
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self.ibus = ibus = wishbone.Interface()
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self.dbus = dbus = wishbone.Interface()
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self.interrupt = Signal(32)
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# Output reset signal -- set to 1 when CPU reset is asserted
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self.debug_reset = Signal()
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verilog_variants = {
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"std": "VexRiscv.v",
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"std_debug": "VexRiscv_Debug.v",
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@ -37,134 +32,136 @@ class VexRiscv(Module, AutoCSR):
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"min": "VexRiscv_Lite.v",
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"min_debug": "VexRiscv_LiteDebug.v",
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}
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cpu_reset = ResetSignal()
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cpu_args = {}
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cpu_filename = verilog_variants[variant]
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if "debug" in variant:
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cpu_reset = Signal()
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cpu_args = {}
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self.i_cmd_valid = Signal()
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self.i_cmd_payload_wr = Signal()
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self.i_cmd_payload_address = Signal(8)
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self.i_cmd_payload_data = Signal(32)
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self.o_cmd_ready = Signal()
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self.o_rsp_data = Signal(32)
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self.o_resetOut = Signal()
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reset_debug_logic = Signal()
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self.transfer_complete = Signal()
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self.transfer_in_progress = Signal()
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self.transfer_wait_for_ack = Signal()
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self.debug_bus = wishbone.Interface()
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self.sync += [
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self.debug_bus.dat_r.eq(self.o_rsp_data),
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cpu_reset.eq(reset_debug_logic | ResetSignal()),
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]
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self.sync += [
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# CYC is held high for the duration of the transfer.
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# STB is kept high when the transfer finishes (write)
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# or the master is waiting for data (read), and stays
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# there until ACK, ERR, or RTY are asserted.
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If((self.debug_bus.stb & self.debug_bus.cyc)
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& (~self.transfer_in_progress)
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& (~self.transfer_complete)
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& (~self.transfer_wait_for_ack),
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self.i_cmd_payload_data.eq(self.debug_bus.dat_w),
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self.i_cmd_payload_address.eq((self.debug_bus.adr[0:6] << 2) | 0),
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self.i_cmd_payload_wr.eq(self.debug_bus.we),
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self.i_cmd_valid.eq(1),
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self.transfer_in_progress.eq(1),
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self.transfer_complete.eq(0),
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self.debug_bus.ack.eq(0)
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).Elif(self.transfer_in_progress,
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If(self.o_cmd_ready,
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self.i_cmd_valid.eq(0),
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self.i_cmd_payload_wr.eq(0),
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self.transfer_complete.eq(1),
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self.transfer_in_progress.eq(0)
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)
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).Elif(self.transfer_complete,
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self.transfer_complete.eq(0),
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self.debug_bus.ack.eq(1),
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self.transfer_wait_for_ack.eq(1)
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).Elif(self.transfer_wait_for_ack & ~(self.debug_bus.stb & self.debug_bus.cyc),
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self.transfer_wait_for_ack.eq(0),
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self.debug_bus.ack.eq(0)
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),
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# Force a Wishbone error if transferring during a reset sequence.
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# Because o_resetOut is multiple cycles and i.stb/d.stb should
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# deassert one cycle after i_err/i_ack/d_err/d_ack are asserted,
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# this will give i_err and o_err enough time to be reset to 0
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# once the reset cycle finishes.
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If(self.o_resetOut,
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If(i.cyc & i.stb, i_err.eq(1)).Else(i_err.eq(0)),
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If(d.cyc & d.stb, d_err.eq(1)).Else(d_err.eq(0)),
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reset_debug_logic.eq(1))
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.Else(
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reset_debug_logic.eq(0)
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)
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]
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cpu_args.update({
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"i_debugReset": ResetSignal(),
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"i_debug_bus_cmd_valid": self.i_cmd_valid,
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"i_debug_bus_cmd_payload_wr": self.i_cmd_payload_wr,
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"i_debug_bus_cmd_payload_address": self.i_cmd_payload_address,
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"i_debug_bus_cmd_payload_data": self.i_cmd_payload_data,
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"o_debug_bus_cmd_ready": self.o_cmd_ready,
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"o_debug_bus_rsp_data": self.o_rsp_data,
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"o_debug_resetOut": self.o_resetOut
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})
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self.comb += [
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i.err.eq(i_err),
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d.err.eq(d_err),
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]
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self.specials += Instance("VexRiscv",
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**cpu_args,
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self.cpu_params = dict(
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i_clk=ClockSignal(),
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i_reset=cpu_reset | self.reset,
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i_reset=ResetSignal() | self.reset,
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i_externalResetVector=cpu_reset_address,
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i_externalInterruptArray=self.interrupt,
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i_timerInterrupt=0,
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o_iBusWishbone_ADR=i.adr,
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o_iBusWishbone_DAT_MOSI=i.dat_w,
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o_iBusWishbone_SEL=i.sel,
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o_iBusWishbone_CYC=i.cyc,
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o_iBusWishbone_STB=i.stb,
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o_iBusWishbone_WE=i.we,
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o_iBusWishbone_CTI=i.cti,
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o_iBusWishbone_BTE=i.bte,
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i_iBusWishbone_DAT_MISO=i.dat_r,
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i_iBusWishbone_ACK=i.ack,
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i_iBusWishbone_ERR=i_err,
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o_iBusWishbone_ADR=ibus.adr,
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o_iBusWishbone_DAT_MOSI=ibus.dat_w,
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o_iBusWishbone_SEL=ibus.sel,
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o_iBusWishbone_CYC=ibus.cyc,
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o_iBusWishbone_STB=ibus.stb,
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o_iBusWishbone_WE=ibus.we,
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o_iBusWishbone_CTI=ibus.cti,
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o_iBusWishbone_BTE=ibus.bte,
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i_iBusWishbone_DAT_MISO=ibus.dat_r,
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i_iBusWishbone_ACK=ibus.ack,
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i_iBusWishbone_ERR=ibus.err,
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o_dBusWishbone_ADR=d.adr,
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o_dBusWishbone_DAT_MOSI=d.dat_w,
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o_dBusWishbone_SEL=d.sel,
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o_dBusWishbone_CYC=d.cyc,
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o_dBusWishbone_STB=d.stb,
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o_dBusWishbone_WE=d.we,
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o_dBusWishbone_CTI=d.cti,
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o_dBusWishbone_BTE=d.bte,
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i_dBusWishbone_DAT_MISO=d.dat_r,
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i_dBusWishbone_ACK=d.ack,
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i_dBusWishbone_ERR=d_err)
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o_dBusWishbone_ADR=dbus.adr,
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o_dBusWishbone_DAT_MOSI=dbus.dat_w,
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o_dBusWishbone_SEL=dbus.sel,
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o_dBusWishbone_CYC=dbus.cyc,
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o_dBusWishbone_STB=dbus.stb,
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o_dBusWishbone_WE=dbus.we,
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o_dBusWishbone_CTI=dbus.cti,
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o_dBusWishbone_BTE=dbus.bte,
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i_dBusWishbone_DAT_MISO=dbus.dat_r,
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i_dBusWishbone_ACK=dbus.ack,
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i_dBusWishbone_ERR=dbus.err)
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if "debug" in variant:
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self.add_debug()
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# add verilog sources
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self.add_sources(platform, cpu_filename)
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def add_debug(self):
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debug_reset = Signal()
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ibus_err = Signal()
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dbus_err = Signal()
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self.i_cmd_valid = Signal()
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self.i_cmd_payload_wr = Signal()
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self.i_cmd_payload_address = Signal(8)
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self.i_cmd_payload_data = Signal(32)
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self.o_cmd_ready = Signal()
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self.o_rsp_data = Signal(32)
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self.o_resetOut = Signal()
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reset_debug_logic = Signal()
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self.transfer_complete = Signal()
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self.transfer_in_progress = Signal()
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self.transfer_wait_for_ack = Signal()
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self.debug_bus = wishbone.Interface()
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self.sync += [
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self.debug_bus.dat_r.eq(self.o_rsp_data),
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debug_reset.eq(reset_debug_logic | ResetSignal()),
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]
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self.sync += [
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# CYC is held high for the duration of the transfer.
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# STB is kept high when the transfer finishes (write)
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# or the master is waiting for data (read), and stays
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# there until ACK, ERR, or RTY are asserted.
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If((self.debug_bus.stb & self.debug_bus.cyc)
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& (~self.transfer_in_progress)
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& (~self.transfer_complete)
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& (~self.transfer_wait_for_ack),
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self.i_cmd_payload_data.eq(self.debug_bus.dat_w),
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self.i_cmd_payload_address.eq((self.debug_bus.adr[0:6] << 2) | 0),
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self.i_cmd_payload_wr.eq(self.debug_bus.we),
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self.i_cmd_valid.eq(1),
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self.transfer_in_progress.eq(1),
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self.transfer_complete.eq(0),
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self.debug_bus.ack.eq(0)
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).Elif(self.transfer_in_progress,
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If(self.o_cmd_ready,
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self.i_cmd_valid.eq(0),
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self.i_cmd_payload_wr.eq(0),
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self.transfer_complete.eq(1),
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self.transfer_in_progress.eq(0)
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)
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).Elif(self.transfer_complete,
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self.transfer_complete.eq(0),
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self.debug_bus.ack.eq(1),
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self.transfer_wait_for_ack.eq(1)
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).Elif(self.transfer_wait_for_ack & ~(self.debug_bus.stb & self.debug_bus.cyc),
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self.transfer_wait_for_ack.eq(0),
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self.debug_bus.ack.eq(0)
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),
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# Force a Wishbone error if transferring during a reset sequence.
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# Because o_resetOut is multiple cycles and i.stb/d.stb should
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# deassert one cycle after i_err/i_ack/d_err/d_ack are asserted,
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# this will give i_err and o_err enough time to be reset to 0
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# once the reset cycle finishes.
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If(self.o_resetOut,
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If(self.ibus.cyc & self.ibus.stb, ibus_err.eq(1)).Else(ibus_err.eq(0)),
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If(self.dbus.cyc & self.dbus.stb, dbus_err.eq(1)).Else(dbus_err.eq(0)),
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reset_debug_logic.eq(1))
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.Else(
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reset_debug_logic.eq(0)
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)
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]
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self.cpu_params.update(
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i_reset=ResetSignal() | self.reset | debug_reset,
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i_iBusWishbone_ERR=self.ibus.err | ibus_err,
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i_dBusWishbone_ERR=self.dbus.err | dbus_err,
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i_debugReset=ResetSignal(),
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i_debug_bus_cmd_valid=self.i_cmd_valid,
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i_debug_bus_cmd_payload_wr=self.i_cmd_payload_wr,
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i_debug_bus_cmd_payload_address=self.i_cmd_payload_address,
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i_debug_bus_cmd_payload_data=self.i_cmd_payload_data,
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o_debug_bus_cmd_ready=self.o_cmd_ready,
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o_debug_bus_rsp_data=self.o_rsp_data,
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o_debug_resetOut=self.o_resetOut
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)
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@staticmethod
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def add_sources(platform, cpu_filename):
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vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
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platform.add_source(os.path.join(vdir, cpu_filename))
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def do_finalize(self):
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self.specials += Instance("VexRiscv", **self.cpu_params)
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