migen/fhdl: pass fdict filename --> contents to specials

This commit is contained in:
Florent Kermarrec 2015-03-30 11:09:29 +02:00
parent f03aa76292
commit ea04947519
2 changed files with 17 additions and 15 deletions

View File

@ -48,7 +48,7 @@ class Tristate(Special):
yield self, attr, target_context
@staticmethod
def emit_verilog(tristate, ns):
def emit_verilog(tristate, ns, fdict):
def pe(e):
return verilog_printexpr(ns, e)[0]
w, s = value_bits_sign(tristate.target)
@ -58,7 +58,7 @@ class Tristate(Special):
if tristate.i is not None:
r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n"
r += "\n"
return r
return r, fdict
class TSTriple:
def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0):
@ -123,7 +123,7 @@ class Instance(Special):
yield item, "expr", SPECIAL_INOUT
@staticmethod
def emit_verilog(instance, ns):
def emit_verilog(instance, ns, fdict):
r = instance.of + " "
parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items))
if parameters:
@ -165,7 +165,7 @@ class Instance(Special):
r += ")" + synthesis_directive + ";\n\n"
else:
r += ");\n\n"
return r
return r, fdict
(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
@ -198,8 +198,8 @@ class _MemoryPort(Special):
yield self, attr, target_context
@staticmethod
def emit_verilog(port, ns):
return "" # done by parent Memory object
def emit_verilog(port, ns, fdict):
return "", fdict # done by parent Memory object
class Memory(Special):
def __init__(self, width, depth, init=None, name=None):
@ -237,7 +237,7 @@ class Memory(Special):
return mp
@staticmethod
def emit_verilog(memory, ns):
def emit_verilog(memory, ns, fdict):
r = ""
def gn(e):
if isinstance(e, Memory):
@ -320,8 +320,7 @@ class Memory(Special):
r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
r += "end\n\n"
return r
return r, fdict
class SynthesisDirective(Special):
def __init__(self, template, **signals):
@ -330,7 +329,7 @@ class SynthesisDirective(Special):
self.signals = signals
@staticmethod
def emit_verilog(directive, ns):
def emit_verilog(directive, ns, fdict):
name_dict = dict((k, ns.get_name(sig)) for k, sig in directive.signals.items())
formatted = directive.template.format(**name_dict)
return "// synthesis " + formatted + "\n"
return "// synthesis " + formatted + "\n", fdict

View File

@ -1,5 +1,6 @@
from functools import partial
from operator import itemgetter
from collections import OrderedDict
from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
@ -257,14 +258,14 @@ def _lower_specials(overrides, specials):
f.specials -= lowered_specials2
return f, lowered_specials
def _printspecials(overrides, specials, ns):
def _printspecials(overrides, specials, ns, fdict):
r = ""
for special in sorted(specials, key=lambda x: x.huid):
pr = _call_special_classmethod(overrides, special, "emit_verilog", ns)
pr, fdict = _call_special_classmethod(overrides, special, "emit_verilog", ns, fdict)
if pr is None:
raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
r += pr
return r
return r, fdict
class VerilogConvert:
def __init__(self, f, ios=None, name="top",
@ -311,7 +312,9 @@ class VerilogConvert:
r += _printheader(self.f, self.ios, self.name, self.ns)
r += _printcomb(self.f, self.ns, self.display_run)
r += _printsync(self.f, self.ns)
r += _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns)
fdict = OrderedDict()
src, fdict = _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns, fdict)
r += src
r += "endmodule\n"
return r