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fix phy datapath, first communications between SATACON and a HDD... :)

This commit is contained in:
Florent Kermarrec 2014-12-19 20:16:37 +01:00
parent a79696641a
commit ea2b06b285
3 changed files with 21 additions and 8 deletions
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22
lib/sata/phy/datapath.py
View File

@ -12,25 +12,30 @@ class SATAPHYDatapathRX(Module):
### ###
# width convertion (16 to 32) and byte alignment # width convertion (16 to 32) and byte alignment
byte_alignment = Signal()
last_charisk = Signal(2) last_charisk = Signal(2)
last_data = Signal(16) last_data = Signal(16)
self.sync += \ self.sync.sata_rx += \
If(self.sink.stb & self.sink.ack, If(self.sink.stb & self.sink.ack,
If(self.sink.charisk != 0, If(self.sink.charisk != 0,
last_charisk.eq(self.sink.charisk) byte_alignment.eq(self.sink.charisk[1])
), ),
last_charisk.eq(self.sink.charisk),
last_data.eq(self.sink.data) last_data.eq(self.sink.data)
) )
self.converter = Converter(phy_description(16), phy_description(32), reverse=True) converter = Converter(phy_description(16), phy_description(32), reverse=False)
self.converter = InsertReset(RenameClockDomains(converter, "sata_rx"))
self.comb += [ self.comb += [
self.converter.sink.stb.eq(self.sink.stb), self.converter.sink.stb.eq(self.sink.stb),
self.converter.sink.charisk.eq(0b01), If(byte_alignment,
If(last_charisk[1], self.converter.sink.charisk.eq(Cat(last_charisk[1], self.sink.charisk[0])),
self.converter.sink.data.eq(Cat(self.sink.data[8:], last_data[:8])) self.converter.sink.data.eq(Cat(last_data[8:], self.sink.data[:8]))
).Else( ).Else(
self.converter.sink.charisk.eq(self.sink.charisk),
self.converter.sink.data.eq(self.sink.data) self.converter.sink.data.eq(self.sink.data)
), ),
self.sink.ack.eq(self.converter.sink.ack) self.sink.ack.eq(self.converter.sink.ack),
self.converter.reset.eq(self.converter.source.charisk[2:] != 0)
] ]
# clock domain crossing # clock domain crossing
@ -65,7 +70,8 @@ class SATAPHYDatapathTX(Module):
self.comb += Record.connect(self.sink, fifo.sink) self.comb += Record.connect(self.sink, fifo.sink)
# width convertion (32 to 16) # width convertion (32 to 16)
self.converter = Converter(phy_description(32), phy_description(16), reverse=True) converter = Converter(phy_description(32), phy_description(16), reverse=False)
self.converter = RenameClockDomains(converter, "sata_tx")
self.comb += [ self.comb += [
Record.connect(self.fifo.source, self.converter.sink), Record.connect(self.fifo.source, self.converter.sink),
Record.connect(self.converter.source, self.source) Record.connect(self.converter.source, self.source)

5
targets/test.py
View File

@ -207,6 +207,11 @@ class TestDesign(UART2WB, AutoCSR):
self.sata_phy.sink.data, self.sata_phy.sink.data,
self.sata_phy.sink.charisk, self.sata_phy.sink.charisk,
self.sata_phy.datapath.tx.sink.stb,
self.sata_phy.datapath.tx.sink.data,
self.sata_phy.datapath.tx.sink.charisk,
self.sata_phy.datapath.tx.sink.ack,
self.sata_con.sink.stb, self.sata_con.sink.stb,
self.sata_con.sink.sop, self.sata_con.sink.sop,
self.sata_con.sink.eop, self.sata_con.sink.eop,

2
test/test_identify.py
View File

@ -1,8 +1,10 @@
import time
from config import * from config import *
from miscope.host.drivers import MiLaDriver from miscope.host.drivers import MiLaDriver
mila = MiLaDriver(wb.regs, "mila", use_rle=False) mila = MiLaDriver(wb.regs, "mila", use_rle=False)
wb.open() wb.open()
regs = wb.regs
### ###
trigger0 = mila.sata_con_sink_stb_o*1 trigger0 = mila.sata_con_sink_stb_o*1
mask0 = mila.sata_con_sink_stb_m mask0 = mila.sata_con_sink_stb_m