Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

etherbone_tb OK (will need cleanup)

This commit is contained in:
Florent Kermarrec 2015-02-12 00:01:03 +01:00
parent fca89e8b74
commit ea47037570
2 changed files with 5 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
liteeth/core/etherbone/wishbone.py
View File

@ -58,8 +58,7 @@ class LiteEthEtherboneWishboneMaster(Module):
wr_source.addr.eq(rd_sink.addr),
wr_source.count.eq(rd_sink.count),
wr_source.be.eq(rd_sink.be),
#wr_source.data.eq(data.q),
wr_source.data.eq(0x12345678), # XXX
wr_source.data.eq(data.q),
If(wr_source.stb & wr_source.ack,
rd_sink.ack.eq(1),
If(wr_source.eop,

10
liteeth/test/etherbone_tb.py
View File

@ -51,7 +51,7 @@ class TB(Module):
yield
test_probe = False
test_writes = False
test_writes = True
test_reads = True
# test probe
@ -77,13 +77,12 @@ class TB(Module):
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0
record.byte_enable = 0xf
record.wcount = 16
record.rcount = 0
packet = etherbone.EtherbonePacket()
packet.records = [record]
print(packet)
self.etherbone_model.send(packet)
for i in range(1024):
@ -91,7 +90,7 @@ class TB(Module):
# test reads
if test_reads:
reads = etherbone.EtherboneReads(base_ret_addr=0x2000)
reads = etherbone.EtherboneReads(base_ret_addr=0x1000)
for i in range(16):
reads.add(etherbone.EtherboneRead(i))
record = etherbone.EtherboneRecord()
@ -103,13 +102,12 @@ class TB(Module):
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0
record.byte_enable = 0xf
record.wcount = 0
record.rcount = 16
packet = etherbone.EtherbonePacket()
packet.records = [record]
print(packet)
self.etherbone_model.send(packet)
for i in range(1024):