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add LiteScopeLA example
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parent
5c40ff02cb
commit
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4 changed files with 45 additions and 7 deletions
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@ -139,7 +139,7 @@ class LiteScopeLADriver():
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def build(self):
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for key, value in self.regs.d.items():
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if self.name == key[:len(self.name)]:
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key = key.replace(self.name + "_")
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key = key.replace(self.name + "_", "")
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setattr(self, key, value)
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value = 1
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for name, length in self.layout:
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@ -3,8 +3,6 @@ import os
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib import identifier
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@ -12,7 +10,8 @@ from misoclib import identifier
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from litescope.common import *
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from litescope.bridge.uart2wb import LiteScopeUART2WB
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from litescope.frontend.io import LiteScopeIO
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from litescope.frontend.la import LiteScopeLA
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from litescope.core.trigger import LiteScopeTerm
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class _CRG(Module):
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def __init__(self, clk_in):
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@ -75,11 +74,11 @@ class GenSoC(Module):
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class LiteScopeSoC(GenSoC, AutoCSR):
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default_platform = "de0nano"
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csr_map = {
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"io": 10
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"io": 10,
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"la": 11
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}
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csr_map.update(GenSoC.csr_map)
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def __init__(self, platform, export_mila=False):
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def __init__(self, platform, export_conf=False):
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clk_freq = 50*1000000
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GenSoC.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform.request("clk50"))
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@ -88,4 +87,20 @@ class LiteScopeSoC(GenSoC, AutoCSR):
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self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
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self.comb += self.leds.eq(self.io.o)
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cnt0 = Signal(8)
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cnt1 = Signal(8)
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self.sync += [
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cnt0.eq(cnt0+1),
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cnt1.eq(cnt1+2)
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]
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debug = (
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cnt0,
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cnt1
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)
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self.submodules.la = LiteScopeLA(depth=512, dat=Cat(*debug))
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self.la.add_port(LiteScopeTerm)
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if export_conf:
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self.la.export(self, debug, "./test/la.csv")
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default_subtarget = LiteScopeSoC
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@ -8,3 +8,6 @@ test_regs:
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test_io:
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$(CMD) test_io.py
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test_la:
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$(CMD) test_la.py
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20
test/test_la.py
Normal file
20
test/test_la.py
Normal file
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@ -0,0 +1,20 @@
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from config import *
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from litescope.host.driver import LiteScopeLADriver
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wb.open()
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###
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la = LiteScopeLADriver(wb.regs, "la")
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cond = {"cnt0" : 128} # trigger on cnt0 = 128
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la.prog_term(port=0, cond=cond)
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la.prog_sum("term")
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la.trigger(offset=128, length=256)
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la.wait_done()
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la.read()
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la.export("dump.vcd")
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la.export("dump.csv")
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la.export("dump.py")
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###
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wb.close()
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